公开(公告)号：US08088653B2

公开(公告)日：2012-01-03

申请号：US12604318

申请日：2009-10-22

Applicant: Byoung-June Kim ,  Sung-Hoon Yang ,  Min-Seok Oh ,  Jae-Ho Choi ,  Yong-Mo Choi

Inventor： Byoung-June Kim ,  Sung-Hoon Yang ,  Min-Seok Oh ,  Jae-Ho Choi ,  Yong-Mo Choi

IPC: H01L21/00

CPC classification number: H01L29/78669 ,  H01L27/12 ,  H01L27/124 ,  H01L29/458 ,  H01L29/66765

Abstract: A TFT includes a gate electrode, an active layer, a source electrode, a drain electrode, and a buffer layer. The gate electrode is formed on the substrate; the active layer is formed on the gate electrode. The source and drain electrodes, formed on the active layer, are separated by a predetermined distance. The buffer layer is formed between the active layer and the source and drain electrodes. The buffer layer has a substantially continuously varying content ratio corresponding to a buffer layer thickness. The buffer layer is formed to suppress oxidation of the active layer, and reduce contact resistance.

Abstract translation: TFT包括栅电极，有源层，源电极，漏电极和缓冲层。 栅电极形成在基板上; 在栅电极上形成有源层。 形成在有源层上的源电极和漏电极分开预定的距离。 缓冲层形成在有源层与源极和漏极之间。 缓冲层具有对应于缓冲层厚度的基本连续变化的含量比。 形成缓冲层以抑制有源层的氧化，并降低接触电阻。

公开(公告)号：US08035100B2

公开(公告)日：2011-10-11

申请号：US12197573

申请日：2008-08-25

Applicant: Kap-Soo Yoon ,  Sung-Hoon Yang ,  Byoung-June Kim ,  Czang-Ho Lee ,  Sung-Ryul Kim ,  Hwa-Yeul Oh ,  Jae-Ho Choi ,  Yong-Mo Choi

Inventor： Kap-Soo Yoon ,  Sung-Hoon Yang ,  Byoung-June Kim ,  Czang-Ho Lee ,  Sung-Ryul Kim ,  Hwa-Yeul Oh ,  Jae-Ho Choi ,  Yong-Mo Choi

IPC: H01L29/12

CPC classification number: H01L29/7869 ,  H01L27/1225

Abstract: A thin film transistor substrate includes an insulating plate; a gate electrode disposed on the insulating plate; a semiconductor layer comprising a metal oxide, wherein the metal oxide has oxygen defects of less than or equal to 3%, and wherein the metal oxide comprises about 0.01 mole/cm3 to about 0.3 mole/cm3 of a 3d transition metal; a gate insulating layer disposed between the gate electrode and the semiconductor layer; and a source electrode and a drain electrode disposed on the semiconductor layer. Also described is a display substrate. The metal oxide has oxygen defects of less than or equal to 3%, and is doped with about 0.01 mole/cm3 to about 0.3 mole/cm3 of 3d transition metal. The metal oxide comprises indium oxide or titanium oxide. The 3d transition metal includes at least one 3d transition metal selected from the group consisting of chromium, cobalt, nickel, iron, manganese, and mixtures thereof.

Abstract translation: 薄膜晶体管基板包括绝缘板; 设置在绝缘板上的栅电极; 包含金属氧化物的半导体层，其中所述金属氧化物具有小于或等于3％的氧缺陷，并且其中所述金属氧化物包含约0.01mol / cm 3至约0.3mol / cm 3的3d过渡金属; 设置在所述栅极电极和所述半导体层之间的栅极绝缘层; 以及设置在半导体层上的源电极和漏电极。 还描述了显示基板。 金属氧化物具有小于或等于3％的氧缺陷，并且掺杂有约0.01摩尔/ cm3至约0.3摩尔/ cm3的3d过渡金属。 金属氧化物包括氧化铟或二氧化钛。 3d过渡金属包括选自铬，钴，镍，铁，锰及其混合物中的至少一种3d过渡金属。

公开(公告)号：US20110183463A1

公开(公告)日：2011-07-28

申请号：US12961170

申请日：2010-12-06

Applicant: Sung-Ryul KIM ,  Sung-Hoon YANG ,  Byoung-June KIM ,  Czang-Ho LEE ,  Jae-Ho CHOI ,  Hwa-Yeul OH ,  Yong-Mo CHOI

Inventor： Sung-Ryul KIM ,  Sung-Hoon YANG ,  Byoung-June KIM ,  Czang-Ho LEE ,  Jae-Ho CHOI ,  Hwa-Yeul OH ,  Yong-Mo CHOI

IPC: H01L21/336

CPC classification number: H01L29/78618 ,  H01L29/458 ,  H01L29/66765 ,  H01L29/7869

Abstract: A method of manufacturing a thin film transistor (“TFT”) substrate includes forming a first conductive pattern group including a gate electrode on a substrate, forming a gate insulating layer on the first conductive pattern group, forming a semiconductor layer and an ohmic contact layer on the gate insulating layer by patterning an amorphous silicon layer and an oxide semiconductor layer, forming a second conductive pattern group including a source electrode and a drain electrode on the ohmic contact layer by patterning a data metal layer, forming a protection layer including a contact hole on the second conductive pattern group, and forming a pixel electrode on the contact hole of the protection layer. The TFT substrate including the ohmic contact layer formed of an oxide semiconductor is further provided.

Abstract translation: 制造薄膜晶体管（“TFT”）基板的方法包括在基板上形成包括栅电极的第一导电图案组，在第一导电图案组上形成栅极绝缘层，形成半导体层和欧姆接触层 通过图案化非晶硅层和氧化物半导体层，在栅极绝缘层上，通过图案化数据金属层，在欧姆接触层上形成包括源电极和漏电极的第二导电图案组，形成包括接触的保护层 并且在保护层的接触孔上形成像素电极。 还提供了包括由氧化物半导体形成的欧姆接触层的TFT基板。

公开(公告)号：US07902553B2

公开(公告)日：2011-03-08

申请号：US11930536

申请日：2007-10-31

Applicant: Byoung-June Kim ,  Jae-Ho Choi ,  Chang-Oh Jeong ,  Sung-Hoon Yang ,  Je-Hun Lee ,  Do-Hyun Kim ,  Hwa-Yeul Oh ,  Yong-Mo Choi

Inventor： Byoung-June Kim ,  Jae-Ho Choi ,  Chang-Oh Jeong ,  Sung-Hoon Yang ,  Je-Hun Lee ,  Do-Hyun Kim ,  Hwa-Yeul Oh ,  Yong-Mo Choi

IPC: H01L29/04

CPC classification number: H01L27/1255 ,  H01L27/12 ,  H01L27/1214 ,  H01L27/124 ,  H01L29/41733 ,  H01L29/4908 ,  H01L29/66742 ,  H01L29/66765

Abstract: A manufacturing method of a thin film transistor (TFT) includes forming a gate electrode including a metal that can be combined with silicon to form silicide on a substrate and forming a gate insulation layer by supplying a gas which includes silicon to the gate electrode at a temperature below about 280° C. The method further includes forming a semiconductor on the gate insulation layer, forming a data line and a drain electrode on the semiconductor and forming a pixel electrode connected to the drain electrode.

Abstract translation: 薄膜晶体管（TFT）的制造方法包括形成包括可以与硅组合的金属的栅电极，以在衬底上形成硅化物，并通过在栅极电极中向栅电极提供包括硅的气体形成栅极绝缘层 该方法还包括在栅极绝缘层上形成半导体，在半导体上形成数据线和漏极并形成连接到漏电极的像素电极。

公开(公告)号：US20100270552A1

公开(公告)日：2010-10-28

申请号：US12571323

申请日：2009-09-30

Applicant: Ki-Yong Song ,  Sung-Haeng Cho ,  Jae-Hong Kim ,  Sung-Hen Cho ,  Yong-Mo Choi ,  Hyung-Jun Kim ,  Sung-Ryul Kim ,  Byeong-Hoon Cho ,  O-Sung Seo ,  Seong-Hun Kim

Inventor： Ki-Yong Song ,  Sung-Haeng Cho ,  Jae-Hong Kim ,  Sung-Hen Cho ,  Yong-Mo Choi ,  Hyung-Jun Kim ,  Sung-Ryul Kim ,  Byeong-Hoon Cho ,  O-Sung Seo ,  Seong-Hun Kim

IPC: H01L33/00 ,  B32B37/00 ,  C23F1/00

CPC classification number: C23C18/1608 ,  C23C18/31 ,  H01L21/0271 ,  H01L27/124 ,  H01L27/1288 ,  H01L29/41733 ,  H01L29/458 ,  Y10T156/10

Abstract: A protrusion of dry-etched pattern of a thin film transistor substrate generated due to a difference between isotropy of wet etching and anisotropy of dry etching is removed by forming a plating part on a surface of the wet etched pattern through an electroless plating method. If the plating part is formed on a data pattern layer of the substrate, the width or the thickness of the data pattern layer may be increased without loss of aperture ratio, the channel length of the semiconductor layer may be reduced under the limit according to the stepper resolution and the protrusion part of the semiconductor layer may be removed. As a result, the aperture ratio may be increased, the resistance may be reduced, and the driving margin may be increased due to rising of the ion current. Furthermore, the so-called water-fall noise phenomenon may be eliminated.

Abstract translation: 通过化学镀法在湿蚀刻图案的表面上形成电镀部分，可以消除由于湿蚀刻的各向同性和干蚀刻的各向异性而产生的薄膜晶体管基板的干蚀刻图案的突起。 如果电镀部分形成在基板的数据图案层上，则数据图形层的宽度或厚度可以增加而不损失开口率，半导体层的沟道长度可以在根据 可以去除步进分辨率和半导体层的突起部分。 结果，可以增加开口率，可以降低电阻，并且由于离子电流的上升可能增加驱动裕度。 此外，可以消除所谓的水落噪声现象。

公开(公告)号：US20100062574A1

公开(公告)日：2010-03-11

申请号：US12604318

申请日：2009-10-22

Applicant: Byoung-June KIM ,  Sung-Hoon Yang ,  Min-Seok Oh ,  Jae-Ho Choi ,  Yong-Mo Choi

Inventor： Byoung-June KIM ,  Sung-Hoon Yang ,  Min-Seok Oh ,  Jae-Ho Choi ,  Yong-Mo Choi

IPC: H01L21/336

CPC classification number: H01L29/78669 ,  H01L27/12 ,  H01L27/124 ,  H01L29/458 ,  H01L29/66765

Abstract: A TFT includes a gate electrode, an active layer, a source electrode, a drain electrode, and a buffer layer. The gate electrode is formed on the substrate; the active layer is formed on the gate electrode. The source and drain electrodes, formed on the active layer, are separated by a predetermined distance. The buffer layer is formed between the active layer and the source and drain electrodes. The buffer layer has a substantially continuously varying content ratio corresponding to a buffer layer thickness. The buffer layer is formed to suppress oxidation of the active layer, and reduce contact resistance.

Abstract translation: TFT包括栅电极，有源层，源电极，漏电极和缓冲层。 栅电极形成在基板上; 在栅电极上形成有源层。 形成在有源层上的源电极和漏电极分开预定的距离。 缓冲层形成在有源层与源极和漏极之间。 缓冲层具有对应于缓冲层厚度的基本连续变化的含量比。 形成缓冲层以抑制有源层的氧化，并降低接触电阻。

公开(公告)号：US07615867B2

公开(公告)日：2009-11-10

申请号：US11538394

申请日：2006-10-03

Applicant: Byoung-June Kim ,  Sung-Hoon Yang ,  Min-Seok Oh ,  Jae-Ho Choi ,  Yong-Mo Choi

Inventor： Byoung-June Kim ,  Sung-Hoon Yang ,  Min-Seok Oh ,  Jae-Ho Choi ,  Yong-Mo Choi

IPC: H01L29/417 ,  H01L29/49

CPC classification number: H01L29/78669 ,  H01L27/12 ,  H01L27/124 ,  H01L29/458 ,  H01L29/66765

Abstract: A TFT includes a gate electrode, an active layer, a source electrode, a drain electrode, and a buffer layer. The gate electrode is formed on the substrate; the active layer is formed on the gate electrode. The source and drain electrodes, formed on the active layer, are separated by a predetermined distance. The buffer layer is formed between the active layer and the source and drain electrodes. The buffer layer has a substantially continuously varying content ratio corresponding to a buffer layer thickness. The buffer layer is formed to suppress oxidation of the active layer, and reduce contact resistance.

Abstract translation: TFT包括栅电极，有源层，源电极，漏电极和缓冲层。 栅电极形成在基板上; 在栅电极上形成有源层。 形成在有源层上的源电极和漏电极分开预定的距离。 缓冲层形成在有源层与源极和漏极之间。 缓冲层具有对应于缓冲层厚度的基本连续变化的含量比。 形成缓冲层以抑制有源层的氧化，并降低接触电阻。

公开(公告)号：US07598159B2

公开(公告)日：2009-10-06

申请号：US11746328

申请日：2007-05-09

Applicant: Hwa-yeul Oh ,  Byoung-june Kim ,  Sung-hoon Yang ,  Jae-ho Choi ,  Yong-mo Choi ,  Girotra Kunal

Inventor： Hwa-yeul Oh ,  Byoung-june Kim ,  Sung-hoon Yang ,  Jae-ho Choi ,  Yong-mo Choi ,  Girotra Kunal

IPC: H01L21/00

CPC classification number: H01L27/1214 ,  H01L27/1255 ,  H01L27/1288 ,  H01L29/66765 ,  H01L29/78669 ,  H01L29/78696

Abstract: A method of fabricating a thin film transistor substrate includes forming a gate wiring on an insulating substrate and forming a gate insulating layer on the gate wiring; performing a first hydrogen plasma treatment with respect to the gate insulating layer; forming a first active layer with a first thickness at a first deposition rate on the gate insulating layer; performing a second hydrogen plasma treatment with respect to the first active layer; and forming a second active layer with a second thickness greater than the first thickness at a second deposition rate greater than the first deposition rate, on the first active layer.

Abstract translation: 制造薄膜晶体管基板的方法包括在绝缘基板上形成栅极布线并在栅极布线上形成栅极绝缘层; 对所述栅极绝缘层进行第一氢等离子体处理; 在所述栅绝缘层上以第一沉积速率形成具有第一厚度的第一有源层; 对所述第一活性层进行第二氢等离子体处理; 以及在所述第一活性层上以大于所述第一沉积速率的第二沉积速率形成具有大于所述第一厚度的第二厚度的第二有源层。

公开(公告)号：US20090242881A1

公开(公告)日：2009-10-01

申请号：US12197573

申请日：2008-08-25

Applicant: Kap-Soo YOON ,  Sung-Hoon YANG ,  Byoung-June KIM ,  Czang-Ho LEE ,  Sung-Ryul KIM ,  Hwa-Yeul OH ,  Jae-Ho CHOI ,  Yong-Mo CHOI

Inventor： Kap-Soo YOON ,  Sung-Hoon YANG ,  Byoung-June KIM ,  Czang-Ho LEE ,  Sung-Ryul KIM ,  Hwa-Yeul OH ,  Jae-Ho CHOI ,  Yong-Mo CHOI

IPC: H01L33/00

CPC classification number: H01L29/7869 ,  H01L27/1225

Abstract: A thin film transistor substrate includes an insulating plate; a gate electrode disposed on the insulating plate; a semiconductor layer comprising a metal oxide, wherein the metal oxide has oxygen defects of less than or equal to 3%, and wherein the metal oxide comprises about 0.01 mole/cm3 to about 0.3 mole/cm3 of a 3d transition metal; a gate insulating layer disposed between the gate electrode and the semiconductor layer; and a source electrode and a drain electrode disposed on the semiconductor layer. Also described is a display substrate. The metal oxide has oxygen defects of less than or equal to 3%, and is doped with about 0.01 mole/cm3 to about 0.3 mole/cm3 of 3d transition metal. The metal oxide comprises indium oxide or titanium oxide. The 3d transition metal includes at least one 3d transition metal selected from the group consisting of chromium, cobalt, nickel, iron, manganese, and mixtures thereof.

Abstract translation: 薄膜晶体管基板包括绝缘板; 设置在绝缘板上的栅电极; 包含金属氧化物的半导体层，其中所述金属氧化物具有小于或等于3％的氧缺陷，并且其中所述金属氧化物包含约0.01mol / cm 3至约0.3mol / cm 3的3d过渡金属; 设置在所述栅极电极和所述半导体层之间的栅极绝缘层; 以及设置在半导体层上的源电极和漏电极。 还描述了显示基板。 金属氧化物具有小于或等于3％的氧缺陷，并且掺杂有约0.01摩尔/ cm3至约0.3摩尔/ cm3的3d过渡金属。 金属氧化物包括氧化铟或二氧化钛。 3d过渡金属包括选自铬，钴，镍，铁，锰及其混合物中的至少一种3d过渡金属。

公开(公告)号：US20090152553A1

公开(公告)日：2009-06-18

申请号：US12188956

申请日：2008-08-08

Applicant: Kap-Soo YOON ,  Sung-Hoon Yang ,  Sung-Ryul Kim ,  Hwa-Yeul Oh ,  Jae-Ho Choi ,  Yong-Mo Choi

Inventor： Kap-Soo YOON ,  Sung-Hoon Yang ,  Sung-Ryul Kim ,  Hwa-Yeul Oh ,  Jae-Ho Choi ,  Yong-Mo Choi

IPC: H01L29/04 ,  H01L21/336

CPC classification number: H01L29/78696 ,  B82Y10/00 ,  H01L29/778 ,  H01L29/78687

Abstract: A thin-film transistor (TFT) includes a gate electrode, a semiconductor pattern, a source electrode, and a drain electrode. The semiconductor pattern includes an active layer being overlapped with the gate electrode and a low band gap portion having a lower energy band gap than the active layer. The source and drain electrodes are spaced apart from each other to be overlapped with the semiconductor pattern. Therefore, the semiconductor pattern includes a low band gap portion having a lower energy band gap than the active layer, so that electron mobility may be increased in a channel formed along the low band gap portion so that electric characteristics of the TFT may be enhanced.

Abstract translation: 薄膜晶体管（TFT）包括栅电极，半导体图案，源电极和漏电极。 半导体图案包括与栅电极重叠的有源层和具有比有源层更低的能带隙的低带隙部分。 源极和漏极彼此间隔开以与半导体图案重叠。 因此，半导体图案包括具有比有源层低的能带隙的低带隙部分，使得沿着低带隙部分形成的沟道中的电子迁移率可能增加，从而可以提高TFT的电特性。