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    Border masking structures for liquid crystal displays
    32.
    发明授权
    Border masking structures for liquid crystal displays 有权
    用于液晶显示器的边框掩蔽结构

    公开(公告)号：US09523896B2

    公开(公告)日：2016-12-20

    申请号：US14493151

    申请日：2014-09-22

    Applicant: Apple Inc.

    Inventor： Byung Duk Yang ,  Kwang Soon Park ,  Kyung-Wook Kim ,  Shih Chang Chang

    IPC: G02F1/136 ,  G02F1/1335 ,  G02F1/1333 ,  G02F1/1362 ,  H01L27/12 ,  G02F1/1339

    CPC classification number: G02F1/136209 ,  G02F1/133512 ,  G02F1/1339 ,  G02F2001/133388 ,  H01L27/1218 ,  H01L27/1248 ,  H01L27/1292

    Abstract: A display may have a thin-film transistor (TFT) layer and color filter layer. Light blocking structures in an inactive area of the display may prevent stray backlight from leaking out of the display. The thin-film transistor layer may have a first substrate, a first black masking layer, a planarization layer, and a layer of TFT circuitry on the planarization layer. The color filter layer may have a second substrate and a second black masking layer on the second substrate. Light-cured sealant may be formed between the TFT layer and the color filter layer. Gaps may be formed in the second black masking layer to allow light to cure the sealant. At least a portion of the TFT circuitry may serve to block stray backlight penetrating through the gaps in the second black masking layer during normal operation of the display.

    Abstract translation: 显示器可以具有薄膜晶体管（TFT）层和滤色器层。 显示器的非活动区域中的遮光结构可以防止杂散背光从显示器泄漏出来。 薄膜晶体管层可以在平坦化层上具有第一衬底，第一黑色掩蔽层，平坦化层和TFT电路层。 滤色器层可以在第二基板上具有第二基板和第二黑色掩蔽层。 可以在TFT层和滤色器层之间形成光固化密封剂。 可以在第二黑色掩蔽层中形成间隙以允许光固化密封剂。 至少部分TFT电路可以用于在显示器的正常操作期间阻挡杂散背光穿透第二黑色掩蔽层中的间隙。

    Display With Intraframe Pause Circuitry
    33.
    发明申请
    Display With Intraframe Pause Circuitry 有权
    显示与帧内暂停电路

    公开(公告)号：US20160118011A1

    公开(公告)日：2016-04-28

    申请号：US14520797

    申请日：2014-10-22

    Applicant: Apple Inc.

    Inventor： Kwang Soon Park ,  Chun-Yao Huang ,  Shih Chang Chang

    IPC: G09G3/36 ,  G06F3/041

    CPC classification number: G09G3/3688 ,  G06F3/0412 ,  G06F3/0416 ,  G06F3/044 ,  G09G2300/0814 ,  G09G2300/0819 ,  G09G2300/0842 ,  G09G2310/0267 ,  G09G2310/0286 ,  G09G2310/0294 ,  G09G2310/063 ,  G09G2310/065 ,  G09G2310/08 ,  G09G2320/0209 ,  G11C19/184

    Abstract: A display may have an array of pixels to display images. Gate line driver circuitry may have stages that supply gate line signals. A gate line may be located in each row of the pixels. Each stage may have an output block that produces a respective one of the gate line signals and may have a carry block that separately produces a carry signal that is provided to a later stage in the gate line driver circuitry. A memory may be provided in at least some of the stages to store signals produced by the output blocks during intraframe pausing operations. At the end of an intraframe pause, the stored signals may be used in restarting production of the gate line signals by output blocks in the gate line driver stages. Circuitry may be used to separately reset the output block and suppress carry signal production by the carry block.

    Abstract translation: 显示器可以具有用于显示图像的像素阵列。 栅极线驱动器电路可以具有提供栅极线信号的级。 栅极线可以位于像素的每一行中。 每个级可以具有产生栅极线信号中的相应一个的输出块，并且可以具有分别产生提供给栅极线驱动器电路中的较后级的进位信号的进位块。 可以在至少一些级中提供存储器，以在帧内暂停操作期间存储由输出块产生的信号。 在帧内暂停结束时，存储的信号可以用于通过栅极线驱动器级中的输出块重新开始生成栅极线信号。 可以使用电路来单独复位输出块，并抑制进位块的进位信号产生。

    Display with Low Reflectivity Alignment Structures
    34.
    发明申请
    Display with Low Reflectivity Alignment Structures 有权
    低反射率对准结构的显示

    公开(公告)号：US20160103349A1

    公开(公告)日：2016-04-14

    申请号：US14512677

    申请日：2014-10-13

    Applicant: Apple Inc.

    Inventor： Kwang Soon Park ,  Byung Duk Yang ,  Christopher L. Boitnott ,  Chun-Yao Huang ,  Kuan-Ying Lin ,  Kyung-Wook Kim ,  Mohd Fadzli A. Hassan ,  Shih Chang Chang ,  Supriya Goyal ,  Yong Kwan Kim ,  Yu-Cheng Chen

    IPC: G02F1/1368 ,  G02F1/1335

    CPC classification number: G02F1/133512 ,  G02F1/1309 ,  G02F1/13452 ,  G02F1/13458

    Abstract: A display may have a liquid crystal layer sandwiched between a thin-film transistor layer and a color filter layer. An upper polarizer may be placed on top of the thin-film transistor layer. A lower polarizer may be placed under the color filter layer. Components may be bonded to bond pads on the inner surface of the thin-film transistor layer using anisotropic conductive film. Bond quality may be assessed by probing probe pads that are coupled to the bond pads or by visually inspecting the bond pads through the thin-film transistor layer. Opaque masking material in the inactive area may be provided with openings to accommodate the bond pads. Additional opaque masking material may be placed on the underside of the upper polarizer and on the upper surface of the thin-film transistor layer to block the openings from view following visual inspection.

    Abstract translation: 显示器可以具有夹在薄膜晶体管层和滤色器层之间的液晶层。 上偏振器可以放置在薄膜晶体管层的顶部。 下偏振器可以放置在滤色器层下方。 可以使用各向异性导电膜将部件结合到薄膜晶体管层的内表面上的接合焊盘。 可以通过探测耦合到接合焊盘的探针焊盘或通过目视检查通过薄膜晶体管层的焊盘来评估焊盘质量。 在不活动区域中的不透明掩模材料可以设置有开口以容纳接合焊盘。 附加的不透明掩模材料可以放置在上偏振器的下侧和薄膜晶体管层的上表面上，以在视觉检查之后阻挡开口。

    Displays with multiple refresh rate modes
    37.
    发明授权
    Displays with multiple refresh rate modes 有权

    公开(公告)号：US10923012B1

    公开(公告)日：2021-02-16

    申请号：US16814879

    申请日：2020-03-10

    Applicant: Apple Inc.

    Inventor： Jiaxi Hu ,  Hao-Lin Chiu ,  Shatam Agarwal ,  Kwang Soon Park ,  Joonggun Lee ,  Kyung Wook Kim ,  Shih Chang Chang ,  Fenghua Zheng

    IPC: G09G3/20

    Abstract: An electronic device may include a display. The display may include display driver circuitry that is configured to provide image data to columns of pixels and gate driver circuitry that is configured to provide control signals to rows of pixels. The display may be operable at a native refresh rate that is equal to the highest refresh rate at which the display has full resolution. The display may also be operable in a high refresh rate mode with a high refresh rate that is twice (or some other scaling factor greater than) the native refresh rate. To enable operation at the high refresh rate mode, vertical resolution of the display may be sacrificed. In other words, rows of pixels may be grouped together into effective rows that are then scanned in sequence. The gate driver circuitry may be formed as thin-film transistor circuitry or from gate driver integrated circuits.

    Display having gate lines with zigzag extensions
    38.
    发明授权
    Display having gate lines with zigzag extensions 有权

    公开(公告)号：US10288963B2

    公开(公告)日：2019-05-14

    申请号：US15643367

    申请日：2017-07-06

    Applicant: Apple Inc.

    Inventor： Patrick B. Bennett ,  Kwang Soon Park ,  Chun-Yao Huang ,  Byung Duk Yang ,  Shih Chang Chang

    IPC: G06F3/038 ,  G09G5/00 ,  G02F1/1362 ,  H01L27/12 ,  G09G3/20 ,  G02F1/1345

    Abstract: A display may have an array of pixels arranged in rows and columns. Display driver circuitry may be provided along an edge of the display. Data lines that are associated with columns of the pixels may be used to distribute data from the display driver circuitry to the pixels. Gate lines in the display may each have a horizontal straight portion that extends along a respective row of the pixels and may each have one or more non-horizontal segments such as zigzag segments. The non-horizontal portion of each gate line may be connected to the horizontal straight portion of the gate line by a via. The non-horizontal portions may each have portions that are overlapped by portions of the data lines. Dummy gate line structures may be provided on the display that are not coupled to any of the pixels in the display.

    Clock and Signal Distribution Circuitry for Displays
    39.
    发明申请
    Clock and Signal Distribution Circuitry for Displays 审中-公开

    公开(公告)号：US20180308445A1

    公开(公告)日：2018-10-25

    申请号：US15684109

    申请日：2017-08-23

    Applicant: Apple Inc.

    Inventor： Kwang Soon Park ,  Pei-En Chang ,  Szu-Hsien Lee

    IPC: G09G3/36

    CPC classification number: G09G3/3677 ,  G09G3/3233 ,  G09G2310/08 ,  G09G2320/0219 ,  G09G2320/0223 ,  G09G2320/0233 ,  G09G2330/02

    Abstract: A display may have an array of pixels. Rows of pixels may receive gate line signals over gate lines. Display driver circuitry may have an adjustable clock generator that generates a series of clock pulses with different respective fall times to help equalize kickback voltages in the pixels of different rows. Within each row, gate lines may be provided with multiple parallel lines shorted at a series of tap points to help equalize kickback voltages across the pixels of different columns. A clock path may be formed between the clock generator and gate driver circuits. The clock path may run along an edge of the array of pixels. To help equalize kickback voltages in the pixels of different rows, the clock path may have first and second parallel metal lines that are selectively shorted to each other at a series of tap point locations along the clock path.

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