公开(公告)号：US20190273002A1

公开(公告)日：2019-09-05

申请号：US16417124

申请日：2019-05-20

Applicant: Applied Materials, Inc.

Inventor： Roman GOUK ,  Han-Wen CHEN ,  Steven VERHAVERBEKE ,  Jean DELMAS

IPC: H01L21/67 ,  H01L21/02 ,  H01L21/677 ,  B08B7/00 ,  H01L21/687 ,  F26B21/14 ,  C11D11/00

Abstract: Embodiments described herein generally relate to a processing chamber incorporating a small thermal mass which enable efficient temperature cycling for supercritical drying processes. The chamber generally includes a body, a liner, and an insulation element which enables the liner to exhibit a small thermal mass relative to the body. The chamber is also configured with suitable apparatus for generating and/or maintaining supercritical fluid within a processing volume of the chamber.

公开(公告)号：US20190139788A1

公开(公告)日：2019-05-09

申请号：US16171000

申请日：2018-10-25

Applicant: Applied Materials, Inc.

Inventor： Boyi FU ,  Han-Wen CHEN ,  Kyuil CHO ,  Sivapackia GANAPATHIAPPAN ,  Roman GOUK ,  Steven VERHAVERBEKE ,  Nag B. PATIBANDLA ,  Yan ZHAO ,  Hou T. NG ,  Ankit VORA ,  Daihua ZHANG

IPC: H01L21/56 ,  H01L21/67

Abstract: Aspects of the disclosure generally relate to methods of immobilizing die on a substrate. In one method one or more immobilization features are formed in a selected pattern on a substrate. A die is positioned in contact with the one or more immobilization features and the substrate. The one or more immobilization features are cured, and a mold layer is formed on top of the cured one or more immobilization features and the die so as to encapsulate the die.

公开(公告)号：US20170250094A1

公开(公告)日：2017-08-31

申请号：US15593197

申请日：2017-05-11

Applicant: Applied Materials, Inc.

Inventor： Steven VERHAVERBEKE ,  Han-Wen CHEN ,  Roman GOUK

IPC: H01L21/67 ,  B08B7/00 ,  B08B3/08 ,  H01L21/02 ,  H01L21/677

CPC classification number: H01L21/67034 ,  B08B3/08 ,  B08B7/0021 ,  H01L21/02057 ,  H01L21/02101 ,  H01L21/67051 ,  H01L21/67109 ,  H01L21/67126 ,  H01L21/67742

Abstract: Embodiments of the invention generally relate to a method of cleaning a substrate and a substrate processing apparatus that is configured to perform the method of cleaning the substrate. More specifically, embodiments of the present invention relate to a method of cleaning a substrate in a manner that reduces or eliminates the negative effects of line stiction between semiconductor device features. Other embodiments of the present invention relate to a substrate processing apparatus that allows for cleaning of the substrate in a manner that reduces or eliminates line stiction between semiconductor device features formed on the substrate.

公开(公告)号：US20170098542A1

公开(公告)日：2017-04-06

申请号：US15268180

申请日：2016-09-16

Applicant: Applied Materials, Inc.

Inventor： Roman GOUK ,  Han-Wen CHEN ,  Steven VERHAVERBEKE ,  Jean DELMAS

IPC: H01L21/02 ,  H01L21/687 ,  H01L21/67 ,  B08B3/04

CPC classification number: H01L21/02101 ,  H01L21/02057 ,  H01L21/67034 ,  H01L21/6719 ,  H01L21/68728 ,  H01L21/68785

Abstract: A substrate support apparatus is provided. The apparatus includes a circular base plate and one or more spacers disposed about a circumference of the base plate. The spacers may extend from a top surface of the base plate and a ring body may be coupled to the spacers. The ring body may be spaced from the base plate to define apertures between the base plate and the ring body. One or more support posts may be coupled to the base plate and extend therefrom. The support posts may be coupled to the base plate at positions radially inward from an inner surface of the ring body.

公开(公告)号：US20170098541A1

公开(公告)日：2017-04-06

申请号：US15268162

申请日：2016-09-16

Applicant: Applied Materials, Inc.

Inventor： Roman GOUK ,  Han-Wen CHEN ,  Steven VERHAVERBEKE ,  Jean DELMAS

IPC: H01L21/02 ,  F26B21/14 ,  B08B7/00 ,  F26B5/04

Abstract: A method for processing a substrate is disclosed. The method includes delivering a solvent to a processing chamber and delivering a substrate to the processing chamber. The amount of solvent present in the processing chamber may be configured to submerse the substrate. Liquid CO2 may be delivered to the processing chamber and the liquid CO2 may be mixed with the solvent. Additional liquid CO2 may be delivered to the processing chamber in an amount greater than a volume of the processing chamber to displace the solvent. The liquid CO2 may be phase transitioned to supercritical CO2 in the processing chamber and the substrate may be dried by isothermally depressurizing the processing chamber and exhausting gaseous CO2 from the processing chamber.

公开(公告)号：US20150251214A1

公开(公告)日：2015-09-10

申请号：US14716489

申请日：2015-05-19

Applicant: Applied Materials, Inc.

Inventor： Kurtis LESCHKIES ,  Steven VERHAVERBEKE ,  Robert VISSER

IPC: B05D1/00 ,  D01F1/09 ,  D01D11/06 ,  B05B5/04 ,  D01D5/00

CPC classification number: B05D1/007 ,  B05B5/04 ,  B22F2009/0888 ,  B22F2009/0892 ,  B22F2202/06 ,  D01D5/0061 ,  D01D5/0092 ,  D01D11/06 ,  D01F1/09 ,  D01F6/50

Abstract: Embodiments of the invention generally include apparatus and methods for depositing nanowires in a predetermined pattern during an electrospinning process. An apparatus includes a nozzle for containing and ejecting a deposition material, and a voltage source coupled to the nozzle to eject the deposition material. One or more electric field shaping devices are positioned to shape the electric field adjacent to a substrate to control the trajectory of the ejected deposition material. The electric field shaping device converges an electric field at a point near the surface of the substrate to accurately deposit the deposition material on the substrate in a predetermined pattern. The methods include applying a voltage to a nozzle to eject an electrically-charged deposition material towards a substrate, and shaping one or more electric fields to control the trajectory of the electrically-charged deposition material. The deposition material is then deposited on the substrate in a predetermined pattern.

Abstract translation: 本发明的实施方案通常包括用于在静电纺丝过程期间以预定图案沉积纳米线的装置和方法。 一种装置包括用于容纳和喷射沉积材料的喷嘴，以及耦合到喷嘴以喷射沉积材料的电压源。 定位一个或多个电场成形装置以使与基板相邻的电场成形以控制喷出的沉积材料的轨迹。 电场成形装置在基板表面附近的点收敛电场，以预定图案将沉积材料精确地沉积在基板上。 所述方法包括向喷嘴施加电压以向基板喷射带电荷的沉积材料，以及对一个或多个电场进行整形以控制带电沉积材料的轨迹。 然后将沉积材料以预定图案沉积在基板上。

公开(公告)号：US20140144462A1

公开(公告)日：2014-05-29

申请号：US14078373

申请日：2013-11-12

Applicant: Applied Materials, Inc.

Inventor： Steven VERHAVERBEKE ,  Han-Wen CHEN ,  Roman GOUK

IPC: H01L21/02 ,  H01L21/67

CPC classification number: H01L21/67034 ,  B08B3/08 ,  B08B7/0021 ,  H01L21/02057 ,  H01L21/02101 ,  H01L21/67051 ,  H01L21/67109 ,  H01L21/67126 ,  H01L21/67742

Abstract: Embodiments of the invention generally relate to a method of cleaning a substrate and a substrate processing apparatus that is configured to perform the method of cleaning the substrate. More specifically, embodiments of the present invention relate to a method of cleaning a substrate in a manner that reduces or eliminates the negative effects of line stiction between semiconductor device features. Other embodiments of the present invention relate to a substrate processing apparatus that allows for cleaning of the substrate in a manner that reduces or eliminates line stiction between semiconductor device features formed on the substrate.

Abstract translation: 本发明的实施例一般涉及一种清洁基板的方法和一种被配置为执行清洁基板的方法的基板处理装置。 更具体地，本发明的实施例涉及一种以减少或消除半导体器件特征之间的线状静电的负面影响的方式来清洁衬底的方法。 本发明的其他实施例涉及一种基板处理装置，其能够以减少或消除在基板上形成的半导体器件特征之间的线状静电的方式来清洁基板。

公开(公告)号：US20230282498A1

公开(公告)日：2023-09-07

申请号：US18195234

申请日：2023-05-09

Applicant: Applied Materials, Inc.

Inventor： Kurtis LESCHKIES ,  Jeffrey L. FRANKLIN ,  Wei-Sheng LEI ,  Steven VERHAVERBEKE ,  Jean DELMAS ,  Han-Wen CHEN ,  Giback PARK

IPC: H01L21/67 ,  H01L21/48 ,  B23K26/0622 ,  B23K26/382

CPC classification number: H01L21/67121 ,  H01L21/486 ,  B23K26/0622 ,  B23K26/382 ,  H01L23/49827

Abstract: The present disclosure relates to systems and methods for fabricating semiconductor packages, and more particularly, for forming features in semiconductor packages by laser ablation. In one embodiment, the laser systems and methods described herein can be utilized to pattern a substrate to be utilized as a package frame for a semiconductor package having one or more interconnections formed therethrough and/or one or more semiconductor dies disposed therein. The laser systems described herein can produce tunable laser beams for forming features in a substrate or other package structure. Specifically, frequency, pulse width, pulse shape, and pulse energy of laser beams are tunable based on desired sizes of patterned features and on the material in which the patterned features are formed. The adjustability of the laser beams enables rapid and accurate formation of features in semiconductor substrates and packages with controlled depth and topography.

公开(公告)号：US20220278248A1

公开(公告)日：2022-09-01

申请号：US17747408

申请日：2022-05-18

Applicant: Applied Materials, Inc.

Inventor： Han-Wen CHEN ,  Steven VERHAVERBEKE ,  Giback PARK

IPC: H01L31/18 ,  H01L21/027 ,  H01L21/304 ,  H01L21/768 ,  H01L21/308 ,  H01L21/306

Abstract: The present disclosure relates to methods and apparatus for structuring a semiconductor substrate. In one embodiment, a method of substrate structuring includes applying a resist layer to a substrate optionally disposed on a carrier. The resist layer is patterned using ultraviolet radiation or laser ablation. The patterned portions of the resist layer are then transferred onto the substrate by micro-blasting to form desired features in the substrate while unexposed or un-ablated portions of the resist layer shield the rest of the substrate. The substrate is then exposed to an etch process and a de-bonding process to remove the resist layer and release the carrier.

公开(公告)号：US20210346983A1

公开(公告)日：2021-11-11

申请号：US16871302

申请日：2020-05-11

Applicant: Applied Materials, Inc.

Inventor： Kurtis LESCHKIES ,  Wei-Sheng LEI ,  Jeffrey L. FRANKLIN ,  Jean DELMAS ,  Han-Wen CHEN ,  Giback PARK ,  Steven VERHAVERBEKE

IPC: B23K26/0622 ,  B23K26/382 ,  B23K26/40 ,  H01L21/48 ,  H01L25/00

Abstract: A method of fabricating a frame to enclose one or more semiconductor dies includes forming one or more features including one or more cavities and one or more through-vias in a substrate by a first laser ablation process, filling the one or more through-vias with a dielectric material, and forming a via-in-via in the dielectric material filled in each of the one or more through-vias by a second laser ablation process. The one or more cavities is configured to enclose one or more semiconductor dies therein. In the first laser ablation process, frequency, pulse width, and pulse energy of a first pulsed laser beam to irradiate the substrate are tuned based on a depth of the one or more features. In the second laser ablation process, frequency, pulse width, and pulse energy of a second pulsed laser beam to irradiate the dielectric material are tuned based on a depth of the via-in-via.