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    Technique for monitoring a battery cell
    31.
    发明授权
    Technique for monitoring a battery cell 有权

    公开(公告)号：US11996527B2

    公开(公告)日：2024-05-28

    申请号：US17541000

    申请日：2021-12-02

    Applicant: Arm Limited

    Inventor： Emre Ozer ,  Remy Pottier ,  Jedrzej Kufel ,  John Philip Biggs ,  James Edward Myers

    IPC: H01M10/48 ,  G01R31/392

    CPC classification number: H01M10/482 ,  G01R31/392

    Abstract: A battery cell monitoring system comprises a flexible substrate able to conform to a surface of a battery cell to be monitored, and a plurality of first-level prediction units integrated onto the flexible substrate, where each first-level prediction unit is positioned at a different location on the flexible substrate to each other first-level prediction unit. Each first-level prediction unit comprises at least one sensor to generate sensor signals indicative of a physical state of the battery cell, and first-level prediction circuitry to generate a predicted battery cell status value in dependence on the sensor signals received from the at least one sensor of that first-level prediction unit. Second-level prediction circuitry is arranged to determine a prediction result in dependence on the predicted battery cell status values generated by the first-level prediction circuitry of each first-level prediction unit, and a communications device is used to output the prediction result at least when the prediction result indicates an occurrence of a critical event.

    Systems and Methods of Power Management
    35.
    发明申请
    Systems and Methods of Power Management 有权

    公开(公告)号：US20210208803A1

    公开(公告)日：2021-07-08

    申请号：US16735606

    申请日：2020-01-06

    Applicant: Arm Limited

    Inventor： James Edward Myers ,  Pranay Prabhat ,  Matthew James Walker ,  Parameshwarappa Anand Kumar Savanth ,  Fernando Garcia Redondo

    IPC: G06F3/06 ,  G06F1/3234 ,  G06F1/3221 ,  G06F1/3209

    Abstract: According to one implementation of the present disclosure, a method for power management is disclosed. The method includes: computing, by a central processing unit, software instructions of a software workload in an active-mode operation corresponding to a first operating point on a performance curve of a performance mode; transitioning from instances of the active-mode operation to instances of standby-mode operation of the CPU, and recording, by a time tracking element, each of a plurality of standby entry data points; transitioning from the instances of the standby-mode operation to the instances of the active-mode operation of the CPU, and recording, by the time tracking element, each of a plurality of standby exit data points; and determining a second operating point on the performance curve of the performance mode based on the recorded standby entry data points and the recorded standby exit data points.

    Adapting the usage configuration of integrated circuit input-output pads
    36.
    发明授权
    Adapting the usage configuration of integrated circuit input-output pads 有权

    公开(公告)号：US10996269B2

    公开(公告)日：2021-05-04

    申请号：US15533479

    申请日：2015-12-22

    Applicant: ARM LIMITED

    Inventor： James Edward Myers ,  Parameshwarappa Anand Kumar Savanth

    IPC: G01R31/28 ,  G01R31/317 ,  G06F11/27

    Abstract: Techniques for implementing a self-test procedure of an integrated circuit are provided, where the self-test procedure comprises testing for an electrical connection between first and second input-output pads of the integrated circuit. A control device is capable of adapting a functional configuration of usage of the first and second input-output pads in dependence on presence of the electrical connection. A corresponding integrated circuit, printed circuit and method are also provided. These techniques allow the integrated circuit to be used in a variety of contexts, without requiring physical customisation of the integrated circuit to adapt it to its usage context, in particular where connections from the context to the pads of the integrated circuit may be made to individual pads in some contexts or may span more than one pad in other contexts.

    Clock adjusting techniques
    37.
    发明授权
    Clock adjusting techniques 有权

    公开(公告)号：US10886919B1

    公开(公告)日：2021-01-05

    申请号：US16705099

    申请日：2019-12-05

    Applicant: Arm Limited

    Inventor： James Edward Myers ,  Philex Ming-Yan Fan

    IPC: H03K19/00 ,  G06F1/324 ,  G06F1/14 ,  G06F1/08

    Abstract: Various implementations described herein refer to a method for providing an integrated circuit with a real-time clock source. The method may include generating a real-time clock signal for the integrated circuit with the real-time clock source. The method may include selectively adjusting clock frequency of the real-time clock signal to save power in the integrated circuit.

    Unregulated voltage stacked memory
    39.
    发明授权
    Unregulated voltage stacked memory 有权

    公开(公告)号：US10395724B1

    公开(公告)日：2019-08-27

    申请号：US16011548

    申请日：2018-06-18

    Applicant: Arm Limited

    Inventor： James Edward Myers

    IPC: G11C11/4091 ,  G11C11/4094 ,  G11C7/12 ,  G11C8/08 ,  G11C5/14 ,  G11C11/408 ,  G11C16/30 ,  G11C7/06 ,  G11C11/4074

    Abstract: Methods, systems, and devices supporting unregulated voltage stacked memory are described. A memory device may include one or more memory cells used to store information (e.g., in the form of a logic state) and configured into a number of memory banks. In some embodiments, the memory cells may be stacked. The memory device may also include multiple power supplies, which may be arranged in a series configuration between the memory banks. A memory control logic may be coupled in series with the power supplies and configured to equalize power across stacked memory cells when performing a read operation or a write operation to any of the plurality of stacked memory cells.

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