公开(公告)号：US20210143801A1

公开(公告)日：2021-05-13

申请号：US17157483

申请日：2021-01-25

Applicant: Arm Limited

Inventor： Philex Ming-Yan Fan ,  Parameshwarappa Anand Kumar Savanth ,  Benoit Labbe ,  Bal S. Sandhu ,  Pranay Prabhat ,  James Edward Myers

IPC: H03K3/0231 ,  H02M3/07

Abstract: Various implementations described herein refer to an integrated circuit having a first stage and a second stage. The first stage has a step-down converter coupled to an oscillator between a first voltage supply and a second voltage supply. The second stage is coupled to the first stage, and the second stage has a current bias generator coupled to a diode-connected transistor between the first voltage supply and the second voltage supply. The second stage provides an intermediate voltage to the first stage.

公开(公告)号：US20190304962A1

公开(公告)日：2019-10-03

申请号：US15942132

申请日：2018-03-30

Applicant: Arm Limited

Inventor： Pranay Prabhat ,  James Edward Myers

IPC: H01L27/02 ,  G11C11/412 ,  G11C11/417

Abstract: Various implementations described herein are directed to an integrated circuit having a core array region with an array of memory devices. The integrated circuit may include a periphery region having periphery logic devices that interface with the array of memory devices. The integrated circuit may include a boundary region having one or more buffer devices coupled to body terminals of the periphery logic devices to drive the body terminals of the periphery logic devices using a body biasing signal provided by the one or more buffer devices.

公开(公告)号：US09911510B1

公开(公告)日：2018-03-06

申请号：US15288832

申请日：2016-10-07

Applicant: ARM Limited

Inventor： Jungtae Kwon ,  Young Suk Kim ,  Vivek Nautiyal ,  Pranay Prabhat ,  Fakhruddin Ali Bohra ,  Shri Sagar Dwivedi ,  Satinderjit Singh ,  Lalit Gupta

IPC: G11C29/00 ,  G11C11/418 ,  G11C11/412

CPC classification number: G11C29/76 ,  G11C8/04 ,  G11C11/413 ,  G11C11/418

Abstract: Various implementations described herein are directed to an integrated circuit having a memory cell array with multiple rows of memory cells including at least one redundant row of memory cells. The memory cell array may be partitioned into multiple regions of memory cells including a first region of memory cells corresponding to a first part of the redundant row of memory cells and a second region of memory cells corresponding to a second part of the redundant row of memory cells. The integrated circuit may include wordline driver circuitry coupled to the first and second regions of memory cells and their corresponding first and second parts of the redundant row of memory cells. In some instances, the integrated circuit may include row shift circuitry coupled to the first and second regions of memory cells and their corresponding first and second parts of the redundant row of memory cells.

公开(公告)号：US20170294222A1

公开(公告)日：2017-10-12

申请号：US15093457

申请日：2016-04-07

Applicant: ARM Limited

Inventor： Parameshwarappa Anand Kumar Savanth ,  James Edward Myers ,  Pranay Prabhat ,  David Walter Flynn ,  Shidhartha Das ,  David Michael Bull

IPC: G11C11/419 ,  G11C5/06

CPC classification number: G11C11/419 ,  G11C5/063 ,  G11C11/4125

Abstract: A storage bitcell comprising a first inverter cross-coupled with a second inverter, both the first and second inverter being in a path between a first potential and a second potential; wherein a first isolator is connected in the path between the first inverter and the first potential. The storage bitcell has particular application as Static Random-Access Memory (SRAM) circuitry.