Initialisation of a storage device
    32.
    发明授权

    公开(公告)号:US10964386B2

    公开(公告)日:2021-03-30

    申请号:US16496820

    申请日:2018-03-26

    申请人: Arm Limited

    IPC分类号: G11C7/20 G11C13/00

    摘要: There is provided a system comprising: a storage device having a storage portion comprising a plurality of bitcells coupled to respective first signal lines and second signal lines and control logic to alter a memory state of the plurality of bitcells via the first signal lines and second signal lines; a memory controller coupled to the storage device to transmit one or more initialisation signals to the storage device; wherein the storage device is to initialise the storage portion over a clock cycle in response to the one or more initialisation signals.

    Initialisation of a Storage Device
    34.
    发明申请

    公开(公告)号:US20200286557A1

    公开(公告)日:2020-09-10

    申请号:US16496820

    申请日:2018-03-26

    申请人: Arm Limited

    IPC分类号: G11C13/00

    摘要: There is provided a system comprising: a storage device having a storage portion comprising a plurality of bitcells coupled to respective first signal lines and second signal lines and control logic to alter a memory state of the plurality of bitcells via the first signal lines and second signal lines; a memory controller coupled to the storage device to transmit one or more initialisation signals to the storage device; wherein the storage device is to initialise the storage portion over a clock cycle in response to the one or more initialisation signals.

    Communications device and method
    36.
    发明授权

    公开(公告)号:US10447412B2

    公开(公告)日:2019-10-15

    申请号:US15577487

    申请日:2016-04-15

    申请人: ARM LIMITED

    IPC分类号: H04B7/24 H04B13/00 H04B1/3827

    摘要: A device comprises a coupling configured to couple signals to and from a communications path including at least a part of a human or animal body; a data transmitter coupled to the coupling and configured to transmit, from time to time, a data signal of at least a predetermined temporal duration via the communications path; and a data receiver coupled to the coupling and configured to detect the presence of a signal on the communications path at sets of one or more successive detection instances disposed between successive transmissions of the data signal by the data transmitter, the data receiver being configured so that the successive detection instances of a set are temporally separated by no more than the predetermined temporal duration; the device being configured to initiate a processing operation in response to a detection by the data receiver of the presence of a signal on the communications path.

    Integrated circuit with error repair and fault tolerance
    38.
    发明授权
    Integrated circuit with error repair and fault tolerance 有权
    具有错误修复和容错功能的集成电路

    公开(公告)号:US08862935B2

    公开(公告)日:2014-10-14

    申请号:US14143352

    申请日:2013-12-30

    申请人: ARM Limited

    摘要: An integrated circuit is provided with error detection circuitry and error repair circuitry. Error tolerance circuitry is responsive to a control parameter to selectively disable the error repair circuitry. The control parameter is dependent on the processing performed within the circuit. For example, the control parameter may be generated in dependence upon the program instruction being executed, the output signal value which is in error, the previous behavior of the circuit or in other ways.

    摘要翻译: 集成电路具有错误检测电路和错误修复电路。 误差容限电路响应于控制参数来选择性地禁用错误修复电路。 控制参数取决于电路内执行的处理。 例如,控制参数可以根据执行的程序指令,错误的输出信号值,电路的先前行为或其他方式来生成。