公开(公告)号：US12032487B2

公开(公告)日：2024-07-09

申请号：US17666974

申请日：2022-02-08

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI Technologies ULC

Inventor： Benjamin T. Sander ,  Mark Fowler ,  Anthony Asaro ,  Gongxian Jeffrey Cheng ,  Michael Mantor

IPC: G06F12/10 ,  G06F12/0893 ,  G06F12/1027

CPC classification number: G06F12/1027 ,  G06F12/0893 ,  G06F2212/684

Abstract: A processor maintains an access log indicating a stream of cache misses at a cache of the processor. In response to each of at least a subset of cache misses at the cache, the processor records a corresponding entry in the access log, indicating a physical memory address of the memory access request that resulted in the corresponding miss. In addition, the processor maintains an address translation log that indicates a mapping of physical memory addresses to virtual memory addresses. In response to an address translation (e.g., a page walk) that translates a virtual address to a physical address, the processor stores a mapping of the physical address to the corresponding virtual address at an entry of the address translation log. Software executing at the processor can use the two logs for memory management.

公开(公告)号：US20230401159A1

公开(公告)日：2023-12-14

申请号：US18455479

申请日：2023-08-24

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Anthony Asaro ,  Kevin Normoyle ,  Mark Hummel

IPC: G06F12/1036 ,  G06F12/08 ,  G06F12/06 ,  G06F12/02 ,  G06F12/109

CPC classification number: G06F12/1036 ,  G06F12/08 ,  G06F12/0646 ,  G06F12/0284 ,  G06F12/109 ,  G06F12/10

Abstract: A method and system for providing memory in a computer system. The method includes receiving a memory access request for a shared memory address from a processor, mapping the received memory access request to at least one virtual memory pool to produce a mapping result, and providing the mapping result to the processor.

公开(公告)号：US20220414016A1

公开(公告)日：2022-12-29

申请号：US17355820

申请日：2021-06-23

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： Wade K. Smith ,  Anthony Asaro

IPC: G06F12/0891

Abstract: A translation lookaside buffer (TLB) receives mapping invalidation requests from one or more sources, such as one or more processing units of a processing system. The TLB includes one or more invalidation processing pipelines, wherein each processing pipeline includes multiple processing states arranged in a pipeline, so that a given stage executes its processing operations concurrent with other stages of the pipeline executing their processing operations.

公开(公告)号：US11467870B2

公开(公告)日：2022-10-11

申请号：US16938381

申请日：2020-07-24

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Anirudh R. Acharya ,  Michael J. Mantor ,  Rex Eldon McCrary ,  Anthony Asaro ,  Jeffrey Gongxian Cheng ,  Mark Fowler

IPC: G06F9/46 ,  G06F9/48 ,  G06F9/52 ,  G06F9/54 ,  G06F12/1009 ,  G06F12/14 ,  G06T1/20

Abstract: Systems, apparatuses, and methods for abstracting tasks in virtual memory identifier (VMID) containers are disclosed. A processor coupled to a memory executes a plurality of concurrent tasks including a first task. Responsive to detecting one or more instructions of the first task which correspond to a first operation, the processor retrieves a first identifier (ID) which is used to uniquely identify the first task, wherein the first ID is transparent to the first task. Then, the processor maps the first ID to a second ID and/or a third ID. The processor completes the first operation by using the second ID and/or the third ID to identify the first task to at least a first data structure. In one implementation, the first operation is a memory access operation and the first data structure is a set of page tables. Also, in one implementation, the second ID identifies a first application of the first task and the third ID identifies a first operating system (OS) of the first task.

公开(公告)号：US11288205B2

公开(公告)日：2022-03-29

申请号：US14747980

申请日：2015-06-23

Applicant: Avanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Benjamin T. Sander ,  Mark Fowler ,  Anthony Asaro ,  Gongxian Jeffrey Cheng ,  Mike Mantor

IPC: G06F12/1027 ,  G06F12/0893

Abstract: A processor maintains an access log indicating a stream of cache misses at a cache of the processor. In response to each of at least a subset of cache misses at the cache, the processor records a corresponding entry in the access log, indicating a physical memory address of the memory access request that resulted in the corresponding miss. In addition, the processor maintains an address translation log that indicates a mapping of physical memory addresses to virtual memory addresses. In response to an address translation (e.g., a page walk) that translates a virtual address to a physical address, the processor stores a mapping of the physical address to the corresponding virtual address at an entry of the address translation log. Software executing at the processor can use the two logs for memory management.

公开(公告)号：US10725822B2

公开(公告)日：2020-07-28

申请号：US16050948

申请日：2018-07-31

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Anirudh R. Acharya ,  Michael J. Mantor ,  Rex Eldon McCrary ,  Anthony Asaro ,  Jeffrey Gongxian Cheng ,  Mark Fowler

IPC: G06F9/46 ,  G06F9/48 ,  G06F9/52 ,  G06F9/54 ,  G06F12/1009 ,  G06F12/14 ,  G06T1/20

Abstract: Systems, apparatuses, and methods for abstracting tasks in virtual memory identifier (VMID) containers are disclosed. A processor coupled to a memory executes a plurality of concurrent tasks including a first task. Responsive to detecting one or more instructions of the first task which correspond to a first operation, the processor retrieves a first identifier (ID) which is used to uniquely identify the first task, wherein the first ID is transparent to the first task. Then, the processor maps the first ID to a second ID and/or a third ID. The processor completes the first operation by using the second ID and/or the third ID to identify the first task to at least a first data structure. In one implementation, the first operation is a memory access operation and the first data structure is a set of page tables. Also, in one implementation, the second ID identifies a first application of the first task and the third ID identifies a first operating system (OS) of the first task.

公开(公告)号：US10534730B1

公开(公告)日：2020-01-14

申请号：US16228360

申请日：2018-12-20

Applicant: ATI TECHNOLOGIES ULC

Inventor： Kathirkamanathan Nadarajah ,  Anthony Asaro

IPC: G06F13/16 ,  G06F3/06 ,  G06F9/455

Abstract: A first processor that has a trusted relationship with a trusted memory region (TMR) that includes a first region for storing microcode used to execute a microcontroller on a second processor and a second region for storing data associated with the microcontroller. The microcontroller supports a virtual function that is executed on the second processor. An access controller is configured by the first processor to selectively provide the microcontroller with access to the TMR based on whether the request is to write in the first region. The access controller grants read requests from the microcontroller to read from the first region and denies write requests from the microcontroller to write to the first region. The access controller grants requests from the microcontroller to read from the second region or write to the second region.

公开(公告)号：US20180349165A1

公开(公告)日：2018-12-06

申请号：US15610047

申请日：2017-05-31

Applicant: ATI Technologies ULC

Inventor： Anthony Asaro ,  Gongxian Jeffrey Cheng

IPC: G06F9/455 ,  G06F9/54 ,  G06F9/50 ,  G06F9/52

Abstract: A technique for facilitating direct doorbell rings in a virtualized system is provided. A first device is configured to “ring” a “doorbell” of a second device, where both the first and second devices are not a host processor such as a central processing unit and are coupled to an interconnect fabric such as peripheral component interconnect express (“PCIe”). The first device is configured to ring the doorbell of the second device by writing to a doorbell address in a guest physical address space. For security reasons, a check block checks an offset portion of the doorbell address against a set of allowed doorbell addresses for doorbells specified in the guest physical address space, allowing the doorbell to be written if the doorbell is included in the set of allowed doorbell addresses.

公开(公告)号：US20180307622A1

公开(公告)日：2018-10-25

申请号：US15495707

申请日：2017-04-24

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Wade K. Smith ,  Anthony Asaro

IPC: G06F12/1045 ,  G06F12/1027 ,  G06F12/1009

CPC classification number: G06F12/1063 ,  G06F12/1009 ,  G06F12/1027 ,  G06F2212/65 ,  G06F2212/68

Abstract: Systems, apparatuses, and methods for implementing a virtualized translation lookaside buffer (TLB) are disclosed herein. In one embodiment, a system includes at least an execution unit and a first TLB. The system supports the execution of a plurality of virtual machines in a virtualization environment. The system detects a translation request generated by a first virtual machine with a first virtual memory identifier (VMID). The translation request is conveyed from the execution unit to the first TLB. The first TLB performs a lookup of its cache using at least a portion of a first virtual address and the first VMID. If the lookup misses in the cache, the first TLB allocates an entry which is addressable by the first virtual address and the first VMID, and the first TLB sends the translation request with the first VMID to a second TLB.

公开(公告)号：US20180181488A1

公开(公告)日：2018-06-28

申请号：US15390080

申请日：2016-12-23

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Mark Fowler ,  Jimshed Mirza ,  Anthony Asaro

IPC: G06F12/0804 ,  G06F12/0891 ,  G06F12/1009 ,  G06T1/20 ,  G06T1/60

Abstract: Techniques for performing cache invalidates and write-backs in an accelerated processing device (e.g., a graphics processing device that renders three-dimensional graphics) are disclosed. The techniques involve receiving requests from a “master” (e.g., the central processing unit). The techniques involve invalidating virtual-to-physical address translations in an address translation request. The techniques include splitting up the requests based on whether the requests target virtually or physically tagged caches. Addresses for the portions of a request that target physically tagged caches are translated using invalidated virtual-to-physical address translations for speed. The split up request is processed to generate micro-transactions for individual caches targeted by the request. Micro-transactions for physically and virtually tagged caches are processed in parallel. Once all micro-transactions for a request have been processed, the unit that made the request is notified.