公开(公告)号：US08754794B1

公开(公告)日：2014-06-17

申请号：US13558136

申请日：2012-07-25

申请人： Wei Li ,  Weiqi Ding ,  Wilson Wong

发明人： Wei Li ,  Weiqi Ding ,  Wilson Wong

IPC分类号： H03M1/10

CPC分类号： H03M1/1057 ,  H03M1/1028 ,  H03M1/164

摘要： An integrated circuit with a pipeline analog-to-digital (A/D) converter and associated calibration circuitry is provided. The A/D converter may include multiple series-connected pipeline stages at least some of which are implemented using a switched capacitor configuration. The calibration circuitry may include an analog error correction circuit, a digital error correction circuit, and a calibration control circuit for coordinating the operation of the analog and digital error correction circuits. During calibration operations, the analog error correction circuit may be used to suitably adjust a gain setting for each pipeline stage, whereas the digital error correction circuit may be used to compute a code offset value for each pipeline stage. Calibration may proceed from a least-significant-bit pipeline stage towards a most-significant-bit pipeline stage, one stage at a time.

摘要翻译： 提供了具有管线模数（A / D）转换器和相关校准电路的集成电路。 A / D转换器可以包括多个串联连接的流水线级，其中至少一些使用开关电容器配置来实现。 校准电路可以包括模拟误差校正电路，数字误差校正电路和用于协调模拟和数字纠错电路的操作的校准控制电路。 在校准操作期间，可以使用模拟错误校正电路来适当地调整每个流水线级的增益设置，而数字纠错电路可以用于计算每个流水线级的代码偏移值。 校准可以从最低有效位流水线阶段进入最高有效位流水线阶段，一次一个阶段。

公开(公告)号：US08416001B2

公开(公告)日：2013-04-09

申请号：US13083431

申请日：2011-04-08

申请人： Weiqi Ding ,  Sergey Shumarayev ,  Wilson Wong ,  Tim Tri Hoang ,  Yanjing Ke

发明人： Weiqi Ding ,  Sergey Shumarayev ,  Wilson Wong ,  Tim Tri Hoang ,  Yanjing Ke

IPC分类号： H03K3/017 ,  H03K5/04 ,  H03K7/08

CPC分类号： H03K5/1565 ,  H03K3/017 ,  H03K5/12 ,  H03M9/00

摘要： A transmitter circuit is operable to provide an output signal in response to a first periodic signal. A multiplexer circuit is operable to provide a second periodic signal as a selected signal during a first phase of operation. The multiplexer circuit is operable to provide the output signal of the transmitter circuit as the selected signal during a second phase of operation. A sampler circuit is operable to generate first samples of the selected signal during the first phase of operation. The sampler circuit is operable to generate second samples of the selected signal during the second phase of operation. A duty cycle control circuit is operable to adjust a duty cycle of the first periodic signal based on the first and the second samples.

摘要翻译： 发射机电路可操作以响应于第一周期性信号提供输出信号。 多路复用器电路可操作以在第一操作阶段期间提供作为选定信号的第二周期信号。 多路复用器电路可操作以在第二操作阶段期间将发射机电路的输出信号提供为所选择的信号。 采样器电路可操作以在第一操作阶段产生所选信号的第一采样。 采样器电路可操作以在第二操作阶段期间产生所选信号的第二采样。 占空比控制电路可操作以基于第一和第二采样来调整第一周期信号的占空比。

公开(公告)号：US08290750B1

公开(公告)日：2012-10-16

申请号：US13036437

申请日：2011-02-28

申请人： Wilson Wong ,  Allen Chan ,  Sergey Shumarayev ,  Thungoc M. Tran ,  Tim Tri Hoang ,  Weiqi Ding

发明人： Wilson Wong ,  Allen Chan ,  Sergey Shumarayev ,  Thungoc M. Tran ,  Tim Tri Hoang ,  Weiqi Ding

IPC分类号： H03F1/26

CPC分类号： H03K5/19 ,  H03K19/1774 ,  H03K19/17744 ,  H03K19/1778

摘要： Signal detection circuitry for a serial interface oversamples the input—i.e., samples the input multiple times per clock cycle—so that the likelihood of missing a signal is reduced. Sampling may be done with a regenerative latch which has a large bandwidth and can latch a signal at high speed. The amplitude threshold for detection may be programmable, particularly in a programmable device. Thus, between the use of a regenerative latch which is likely to catch any signal that might be present, and the use of oversampling to avoid the problem of sampling at the wrong time, the likelihood of failing to detect a signal is greatly diminished. Logic, such as a state machine, may be used to determine whether the samples captured s do or do not represent a signal. That logic may be programmable, allowing a user to set various parameters for signal detection.

摘要翻译： 串行接口的信号检测电路对输入进行过采样，即每个时钟周期对输入进行多次采样，从而减少信号丢失的可能性。 可以使用具有大带宽的再生锁存器并且可以高速锁存信号来进行采样。 用于检测的幅度阈值可以是可编程的，特别是在可编程器件中。 因此，在可能捕获可能存在的任何信号的再生锁存器的使用之间以及使用过采样以避免在错误时间采样的问题，大大减少了不能检测信号的可能性。 可以使用诸如状态机的逻辑来确定捕获的样本是否或不表示信号。 该逻辑可以是可编程的，允许用户设置用于信号检测的各种参数。

公开(公告)号：US08230281B2

公开(公告)日：2012-07-24

申请号：US12422916

申请日：2009-04-13

申请人： Sriram Narayan ,  Xiaoyan Su ,  Wilson Wong

发明人： Sriram Narayan ,  Xiaoyan Su ,  Wilson Wong

IPC分类号： G01R31/3177 ,  G01R31/40

CPC分类号： G01R31/318572

摘要： A test driver transmitter drives a test signal through a resistive termination circuit to a first pin to test components on a board during a boundary scan test operation. A test receiver receives the test signal through a second pin and a pass gate coupled to the second pin during the boundary scan test operation. A test signal is transmitted to the test receiver during loopback operation through a loopback circuit.

摘要翻译： 测试驱动器发射器通过电阻终端电路将测试信号驱动到第一引脚，以在边界扫描测试操作期间测试板上的组件。 在边界扫描测试操作期间，测试接收器通过第二引脚和耦合到第二引脚的通过门接收测试信号。 在环回操作期间，通过环回电路将测试信号发送到测试接收机。

公开(公告)号：US07860203B1

公开(公告)日：2010-12-28

申请号：US11725653

申请日：2007-03-19

申请人： Sergey Shumarayev ,  Wilson Wong ,  Tim Tri Hoang ,  Thungoc M. Tran

发明人： Sergey Shumarayev ,  Wilson Wong ,  Tim Tri Hoang ,  Thungoc M. Tran

IPC分类号： H04L7/00

CPC分类号： H03L7/087 ,  H04J3/0688 ,  H04L7/033

摘要： A programmable logic device integrated circuit (“PLD”) includes high-speed serial interface (“HSSI”) circuitry in addition to programmable logic circuitry. The HSSI circuitry includes multiple channels of nominal data-handling circuitry (typically including clock and data recovery (“CDR”) circuitry), and at least one channel of nominal clock management unit (“CMU”) circuitry (typically including phase-locked loop (“PLL”) circuitry or the like). To increase the flexibility with which the channels can be used, the nominal data-handling channels are equipped to alternatively perform CMU-type functions, and the nominal CMU channel is equipped to alternatively perform data-handling functions.

摘要翻译： 可编程逻辑器件集成电路（“PLD”）除了可编程逻辑电路之外还包括高速串行接口（“HSSI”）电路。 HSSI电路包括多个标称数据处理电路（通常包括时钟和数据恢复（“CDR”）电路）的通道，以及标称时钟管理单元（“CMU”）电路的至少一个通道（通常包括锁相环 （“PLL”）电路等）。 为了增加可以使用信道的灵活性，标称数据处理信道被配备为交替执行CMU类型功能，并且标称CMU信道被配备为备选地执行数据处理功能。

公开(公告)号：US07777526B2

公开(公告)日：2010-08-17

申请号：US12134777

申请日：2008-06-06

申请人： Sergey Shumarayev ,  Thungoc M. Tran ,  Wilson Wong ,  Simardeep Maangat

发明人： Sergey Shumarayev ,  Thungoc M. Tran ,  Wilson Wong ,  Simardeep Maangat

IPC分类号： H03K19/094

CPC分类号： H03K19/018514 ,  H03F3/45197 ,  H03F2203/45494 ,  H03F2203/45686

摘要： Signal offset variation caused by transistor variation/mismatch in integrated circuits may be reduced. In one embodiment, a buffer circuit has variable-valued circuit elements. Offset variation measurements are made and the variable-valued circuit elements are calibrated to reduce the measured offset variation. In another embodiment, each amplifying stage of a multi-stage buffer provides variable gain. The total DC gain of the cascade is distributed unevenly across the stages, with more DC gain being provided by amplifier stages at the beginning of the cascade than at the end. An additional pre-amplifier stage can also be provided at the beginning of the cascade.

摘要翻译： 集成电路中晶体管变化/失配引起的信号偏移变化可能会降低。 在一个实施例中，缓冲电路具有可变值电路元件。 进行偏移变化测量，并校准可变值电路元件以减少测量的偏移变化。 在另一个实施例中，多级缓冲器的每个放大级提供可变增益。 级联的总直流增益不均匀地分布在整个级中，在级联开始时比放大器级提供更多的直流增益。 在级联开始时也可以提供一个额外的前级放大器级。

公开(公告)号：US07733982B2

公开(公告)日：2010-06-08

申请号：US12511022

申请日：2009-07-28

申请人： Wilson Wong ,  Rakesh H. Patel ,  Sergey Shumarayev ,  Tin H. Lai

发明人： Wilson Wong ,  Rakesh H. Patel ,  Sergey Shumarayev ,  Tin H. Lai

IPC分类号： H03K9/00 ,  H04L27/00

CPC分类号： H04B7/005 ,  H04L25/03006 ,  H04L25/061

摘要： Systems and methods for adjusting a signal received from a communication path are disclosed. A receiver can receive a signal from a communication path which attenuates at least some frequency components of the signal. The receiver can include an equalization block that adjusts at least some of the frequency content of the received signal, a signal normalization block that provides a normalized signal amplitude and/or a normalized edge slope, and a control block. In one embodiment, the control block controls frequency adjustment in the equalization block for high frequencies but not for low frequencies. For low frequency adjustment, the control block controls the normalized signal amplitude in the signal normalization block. In this manner, controlled adjustment for low frequency content is performed in the signal normalization block.

摘要翻译： 公开了一种用于调整从通信路径接收的信号的系统和方法。 接收机可以接收来自衰减信号的至少一些频率分量的通信路径的信号。 接收机可以包括调整接收信号的频率内容中的至少一些的均衡块，提供归一化信号幅度和/或归一化边沿斜率的信号归一化块以及控制块。 在一个实施例中，控制块控制用于高频而不是低频的均衡块中的频率调整。 对于低频调整，控制块控制信号归一化块中的归一化信号幅度。 以这种方式，在信号归一化块中执行低频内容的受控调整。

公开(公告)号：US07710180B1

公开(公告)日：2010-05-04

申请号：US12116059

申请日：2008-05-06

申请人： Tin H. Lai ,  Wilson Wong

发明人： Tin H. Lai ,  Wilson Wong

IPC分类号： H03F3/45 ,  H03L5/00

CPC分类号： H03F3/45475 ,  H03F3/45192 ,  H03F3/45744 ,  H03F3/45968 ,  H03F2200/321 ,  H03F2203/45212 ,  H03F2203/45646 ,  H03F2203/45678 ,  H03F2203/45681 ,  H03F2203/45726

摘要： Techniques and circuitry are provided for programmably controlling signal offsets in integrated circuitry. In one embodiment, an integrated circuit includes a signal offset cancellation circuit that is programmably selected to control the offset of signals on either one input/output or another input/output of an amplifier circuit. In one embodiment, a logic circuit is used to selectively couple a bank of current sources to one input/output or another input/output of a differential amplifier through a switching circuit. The bank of current sources may employed to control the signal offset on either input/output, or may be decoupled from all of the inputs/outputs when signal offset cancellation is not required.

摘要翻译： 提供技术和电路用于可编程地控制集成电路中的信号偏移。 在一个实施例中，集成电路包括可编程地选择以控制放大器电路的一个输入/输出或另一个输入/输出上的信号的偏移的信号偏移消除电路。 在一个实施例中，逻辑电路用于通过开关电路将一组电流源选择性地耦合到差分放大器的一个输入/输出或另一个输入/输出。 可以采用电流源的组来控制输入/输出上的信号偏移，或者当不需要信号偏移消除时可以与所有的输入/输出去耦。

公开(公告)号：US07697600B2

公开(公告)日：2010-04-13

申请号：US11182658

申请日：2005-07-14

申请人： Simardeep Maangat ,  Sergey Shumarayev ,  Wilson Wong ,  ThuNgoc Tran

发明人： Simardeep Maangat ,  Sergey Shumarayev ,  Wilson Wong ,  ThuNgoc Tran

IPC分类号： H03H7/30

CPC分类号： H04L25/03885 ,  H04B3/04 ,  H04L25/03019

摘要： Data signals transmitted over transmission media suffer from attenuation caused by the transmission media. Equalization circuitry may be provided to compensate for attenuation caused by the transmission media. Equalization circuitry may include multiple stages arranged in series to allow the frequency responses of the stages to aggregate together. Each stage may be programmable to insert a zero, which causes the frequency response of the stage to increase in magnitude by 20 dB/decade. The frequency location of the zero may also be programmable to allow each stage to contribute a certain amount of gain for a specific frequency. Each stage may also be programmable to determine the location of poles for reduction of high frequency noise and cross-talk cancellation.

摘要翻译： 通过传输介质传输的数据信号遭受由传输介质引起的衰减。 可以提供均衡电路以补偿由传输介质引起的衰减。 均衡电路可以包括串联布置的多个级，以允许级的频率响应聚合在一起。 每个级可以是可编程的，以插入一个零，这使得该级的频率响应在幅度上增加20dB /十倍。 零的频率位置也可以是可编程的，以允许每个级对特定频率贡献一定量的增益。 每个阶段也可以被编程以确定用于降低高频噪声和串扰取消的极点的位置。

公开(公告)号：US07675326B1

公开(公告)日：2010-03-09

申请号：US12163709

申请日：2008-06-27

申请人： Mei Luo ,  Sergey Shumarayev ,  Wilson Wong ,  Chong H. Lee

发明人： Mei Luo ,  Sergey Shumarayev ,  Wilson Wong ,  Chong H. Lee

IPC分类号： H03K19/094

CPC分类号： H03K19/00369 ,  H03K19/01812 ,  H03K19/01837 ,  H03K19/018514 ,  H03K19/018585

摘要： Systems and methods are provided using dynamically adjustable differential output drivers. Integrated circuits such as programmable logic devices may be provided with adjustable differential output drivers for transmitting high-speed data to other integrated circuits. The peak-to-peak output voltage and common-mode voltage of the output drivers may be adjusted. Dynamic control circuitry may be used to control the settings of current sources, programmable resistors, and voltage source circuitry in the adjustable differential output driver automatically in real time. The adjustable components in the differential output driver may be adjusted by the dynamic control circuitry based on feedback information received from the integrated circuit to which the data is transmitted.

摘要翻译： 使用动态可调差分输出驱动器提供系统和方法。 诸如可编程逻辑器件的集成电路可以设置有用于将高速数据传输到其他集成电路的可调差分输出驱动器。 可以调整输出驱动器的峰峰值输出电压和共模电压。 动态控制电路可用于实时自动控制可调差分输出驱动器中的电流源，可编程电阻和电压源电路的设置。 基于从发送数据的集成电路接收到的反馈信息，可以通过动态控制电路来调整差分输出驱动器中的可调节部件。