公开(公告)号：US11327882B2

公开(公告)日：2022-05-10

申请号：US16782139

申请日：2020-02-05

Applicant: Allegro MicroSystems, LLC

Inventor： Muhammed Sarwar ,  Vyankatesh Gupta ,  James McClay ,  Sundar Chetlur ,  Harianto Wong ,  Gerardo A. Monreal ,  Nicolás Rafael Biberidis ,  Octavio H. Alpago ,  Nicolas Rigoni

IPC: G06F12/02 ,  G06F9/30 ,  G11C16/26

Abstract: A method comprising: performing a first read from an address in a data storage module by using a first read voltage; storing, in a first register, data that is retrieved from the data storage module as a result of the first read; performing a second read from the address by using a second read voltage; storing, in a second register, data that is retrieved from the data storage module as a result of the second read; detecting whether a weak bit condition is present at the address based on the data that is stored in the first register and the data that is stored in the second register; and correcting the weak bit condition, when the weak bit condition is present at the address.

公开(公告)号：US20220137097A1

公开(公告)日：2022-05-05

申请号：US17648310

申请日：2022-01-19

Applicant: Allegro MicroSystems, LLC

Inventor： Shaun D. Milano ,  Bryan Cadugan ,  Michael C. Doogue ,  Alexander Latham ,  William P. Taylor ,  Harianto Wong ,  Sundar Chetlur

IPC: G01R15/14 ,  G01R15/20 ,  G01R19/00

Abstract: Systems and methods described herein are directed towards integrating a shield layer into a current sensor to shield a magnetic field sensing element and associated circuitry in the current sensor from electrical, voltage, or electrical transient noise. In an embodiment, a shield layer may be disposed along at least one surface of a die supporting a magnetic field sensing element. The shield layer may be disposed in various arrangements to shunt noise caused by a parasitic coupling between the magnetic field sensing element and the current carrying conductor away from the magnetic field sensing element.

公开(公告)号：US20220115316A1

公开(公告)日：2022-04-14

申请号：US17067178

申请日：2020-10-09

Applicant: Allegro MicroSystems, LLC

Inventor： Sundar Chetlur ,  Maxim Klebanov ,  Cory Voisine ,  Kenneth Snowdon ,  Hsuan-Jung Wu

IPC: H01L23/522 ,  H01L21/8234

Abstract: An apparatus, comprising: a substrate; a coupling capacitor that is formed over the substrate; and an isolator that is formed between the substrate and the coupling capacitor, the isolator including: (a) an MP-well layer, (b) a first well layer, (c) an epi tub layer that is nested in the MP-well layer and the first well layer, and (d) a second well layer that is nested in the epi tub layer.

公开(公告)号：US20210295932A1

公开(公告)日：2021-09-23

申请号：US16822119

申请日：2020-03-18

Applicant: Allegro MicroSystems, LLC

Inventor： Muhammad Sarwar ,  Vyankatesh Gupta ,  James McClay ,  Sundar Chetlur ,  Harianto Wong

IPC: G11C16/34 ,  G11C16/14 ,  G11C16/26 ,  G11C16/08 ,  G11C11/406 ,  G11C11/4074 ,  G11C5/05 ,  G01R33/09

Abstract: A method for use in a memory device including a first memory matrix is provided, the method comprising: receiving a write request that is associated with a first memory cell, the first memory cell being part of the first memory matrix; copying a content of a second memory cell into a register, the second memory cell being part of the first memory matrix; overwriting the second memory cell with the content of the register when the content of the second memory cell is different from the content of the register; and writing, to the first memory cell, at least a portion of data that is associated with the write request.

公开(公告)号：US20210240606A1

公开(公告)日：2021-08-05

申请号：US16782139

申请日：2020-02-05

Applicant: Allegro MicroSystems, LLC

Inventor： Muhammed Sarwar ,  Vyankatesh Gupta ,  James McClay ,  Sundar Chetlur ,  Harianto Wong ,  Gerardo A. Monreal ,  Nicolás Rafael Biberidis ,  Octavio H. Alpago ,  Nicolas Rigoni

IPC: G06F12/02 ,  G06F9/30 ,  G11C16/26

Abstract: A method comprising: performing a first read from an address in a data storage module by using a first read voltage; storing, in a first register, data that is retrieved from the data storage module as a result of the first read; performing a second read from the address by using a second read voltage; storing, in a second register, data that is retrieved from the data storage module as a result of the second read; detecting whether a weak bit condition is present at the address based on the data that is stored in the first register and the data that is stored in the second register; and correcting the weak bit condition, when the weak bit condition is present at the address.

公开(公告)号：US10916438B2

公开(公告)日：2021-02-09

申请号：US16407500

申请日：2019-05-09

Applicant: Allegro MicroSystems, LLC

Inventor： Maxim Klebanov ,  Sundar Chetlur ,  James McClay

IPC: H01L21/8238 ,  H01L21/8234 ,  H01L21/336 ,  H01L21/308 ,  H01L21/033 ,  H01L29/51

Abstract: Methods for fabricating an integrated circuit having a plurality of gate dielectrics. The methods are provided to include: forming one or more isolation trenches and a first active region and a second active region in a substrate; depositing hard mask material on the substrate; removing a first portion of the hard mask material over the first active region; forming a first oxide layer having a first thickness over the first active region; removing a second portion of the hard mask material over the second active region; and forming a second oxide layer having a second thickness over the first and second active regions such that a thickness of oxide formed over the first active region comprises a sum of the thickness of the first oxide layer and the second oxide layer, and a thickness of oxide formed over the second active region comprises the second thickness.

公开(公告)号：US20200076189A1

公开(公告)日：2020-03-05

申请号：US16115901

申请日：2018-08-29

Applicant: Allegro MicroSystems, LLC

Inventor： Washington Lamar ,  Maxim Klebanov ,  Sundar Chetlur

IPC: H02H9/04 ,  H02H1/00

Abstract: An electronic device having first and second terminals includes an electrical overstress (EOS) protection circuitry configured to detect an EOS event at one or both of the first and second terminals. The electronic device includes a power clamp coupled to the EOS protection circuitry and configured to clamp a voltage between the first terminal and the second terminal to a clamp voltage. The EOS protection circuitry can adjust the clamp voltage when an EOS event is detected.

公开(公告)号：US20180342500A1

公开(公告)日：2018-11-29

申请号：US15606043

申请日：2017-05-26

Applicant: Allegro Microsystems, LLC

Inventor： Sundar Chetlur ,  Maxim Klebanov ,  Washington Lamar

IPC: H01L27/02 ,  H01L29/423 ,  H01L27/088 ,  H01L29/78 ,  H01L29/51 ,  H01L43/06 ,  H01L43/10 ,  H01L29/06 ,  H01L29/08

Abstract: A metal-oxide semiconductor (MOS) transistor structure is provided herein having one or more horizontal and/or one or more vertical MOS transistor structures formed around trench and liner isolation regions. The trench region serves as a gate electrode, while the liner is formed around the sidewalls of trench region and serves as a gate dielectric of a parasitic MOS within the transistor structure. The MOS transistor structure includes various doped regions formed around one or more portions of the trench and liner regions. The doped regions can have one or more different doping types such that in response to a voltage applied to the trench region, a channel region is formed in at least one of the doped regions and provides a current path within the MOS transistor between different doped regions.

公开(公告)号：US12210040B2

公开(公告)日：2025-01-28

申请号：US17648310

申请日：2022-01-19

Applicant: Allegro MicroSystems, LLC

Inventor： Shaun D. Milano ,  Bryan Cadugan ,  Michael C. Doogue ,  Alexander Latham ,  William P. Taylor ,  Harianto Wong ,  Sundar Chetlur

IPC: G01R15/14 ,  G01R15/20 ,  G01R19/00

Abstract: Systems and methods described herein are directed towards integrating a shield layer into a current sensor to shield a magnetic field sensing element and associated circuitry in the current sensor from electrical, voltage, or electrical transient noise. In an embodiment, a shield layer may be disposed along at least one surface of a die supporting a magnetic field sensing element. The shield layer may be disposed in various arrangements to shunt noise caused by a parasitic coupling between the magnetic field sensing element and the current carrying conductor away from the magnetic field sensing element.

公开(公告)号：US12068237B2

公开(公告)日：2024-08-20

申请号：US18051151

申请日：2022-10-31

Applicant: Allegro MicroSystems, LLC

Inventor： Sundar Chetlur ,  Maxim Klebanov ,  Cory Voisine ,  Kenneth Snowdon ,  Hsuan-Jung Wu

IPC: H01L23/52 ,  H01L21/8234 ,  H01L23/522

CPC classification number: H01L23/5222 ,  H01L21/823493

Abstract: An apparatus including; a substrate; an isolator that is formed over the substrate, the isolator including a silicon shield layer that is formed between a first buried oxide (BOX) layer and a second BOX layer; a silicon layer having an oxide trench structure formed therein, the oxide trench structure being arranged to define a first silicon island and a second silicon island; a first electronic circuit that is formed over the first silicon island; and a second electronic circuit that is formed over the second silicon island, the first electronic circuit being electrically coupled to the first electronic circuit.