公开(公告)号：US08325861B2

公开(公告)日：2012-12-04

申请号：US13341612

申请日：2011-12-30

申请人： Kun-Yung Chang ,  Fariborz Assaderaghi

发明人： Kun-Yung Chang ,  Fariborz Assaderaghi

IPC分类号： H04L25/08

CPC分类号： H03L7/00 ,  H03L7/06

摘要： A circuit includes a frequency synthesizer, N phase mixers coupled to the frequency synthesizer, a plurality of receivers, and a calibration circuit. The frequency synthesizer is to receive a reference clock signal and is to output a primary clock signal. A respective phase mixer in the N phase mixers is to output a respective secondary clock signal having a corresponding phase. A respective receiver in the plurality of receivers is coupled to two of the N phase mixers, and at a respective time is to receive data in accordance with the respective secondary clock signal from one of the two phase mixers coupled to the respective receiver. The calibration circuit is to calibrate a secondary clock signal output by a respective phase mixer in the N phase mixers by adjusting the phase of the secondary clock signal of the respective phase mixer.

公开(公告)号：US20100239057A1

公开(公告)日：2010-09-23

申请号：US12787352

申请日：2010-05-25

申请人： Kun-Yung Chang ,  Fariborz Assaderaghi

发明人： Kun-Yung Chang ,  Fariborz Assaderaghi

IPC分类号： H04B1/10

CPC分类号： H03L7/00 ,  H03L7/06

摘要： A circuit includes a frequency synthesizer, N phase mixers coupled to the frequency synthesizer, a plurality of receivers, and a calibration circuit. The frequency synthesizer is to receive a reference clock signal and is to output a primary clock signal. A respective phase mixer in the N phase mixers is to output a respective secondary clock signal having a corresponding phase. A respective receiver in the plurality of receivers is coupled to two of the N phase mixers, and at a respective time is to receive data in accordance with the respective secondary clock signal from one of the two phase mixers coupled to the respective receiver. The calibration circuit is to calibrate a secondary clock signal output by a respective phase mixer in the N phase mixers by adjusting the phase of the secondary clock signal of the respective phase mixer.

摘要翻译： 电路包括频率合成器，耦合到频率合成器的N相混频器，多个接收器和校准电路。 频率合成器是接收参考时钟信号，并输出主时钟信号。 N相混频器中的相应的混频器将输出具有相应相位的相应次级时钟信号。 多个接收机中的相应接收机耦合到N相混合器中的两个，并且在相应的时间是根据耦合到相应接收机的两个相位混合器之一的相应辅助时钟信号接收数据。 校准电路是通过调整相位相位混合器的次级时钟信号的相位来校准由N相混频器中的各个相位混频器输出的次级时钟信号。

公开(公告)号：US20070147569A1

公开(公告)日：2007-06-28

申请号：US11685017

申请日：2007-03-12

申请人： Kun-Yung Chang ,  Kevin Donnelly

发明人： Kun-Yung Chang ,  Kevin Donnelly

IPC分类号： H03D3/24

CPC分类号： H04L7/0337 ,  H03L7/07 ,  H03L7/0814 ,  H03L7/091 ,  H04L7/0025

摘要： An integrated circuit device having a selectable data rate clock data recovery (CDR) circuit and a selectable data rate transmit circuit. The CDR circuit includes a receive circuit to capture a plurality of samples of an input signal during a cycle of a first clock signal. A select circuit is coupled to the receive circuit to select, according to a receive data rate select signal, one of the plurality of samples to be a first selected sample of the input signal and another of the plurality of samples to be a second selected sample of the input signal. A phase control circuit is coupled to receive the first and second selected samples of the input signal and includes circuitry to compare the selected samples to determine whether the first clock signal leads or lags a transition of the input signal. The transmit circuit includes a serializing circuit to receive a parallel set of bits and to output the set of bits in sequence to an output driver in response to a first clock signal. A select circuit selects, according to a transmit data rate select signal, data bits within an outbound data value to form the parallel set of bits received within the serializing circuit. Bits within the outbound data value are selected to achieve a first data rate when the transmit data rate select signal is in a first state, and to achieve a second data rate when the transmit data rate select signal is in a second state.

摘要翻译： 一种具有可选数据速率时钟数据恢复（CDR）电路和可选数据速率发射电路的集成电路装置。 CDR电路包括在第一时钟信号的周期期间捕获输入信号的多个采样的接收电路。 选择电路耦合到接收电路，以根据接收数据速率选择信号选择多个采样中的一个作为输入信号的第一选定采样，并将多个样本中的另一个作为第二选定采样 的输入信号。 相位控制电路被耦合以接收输入信号的第一和第二选定采样，并且包括用于比较所选择的采样以确定第一时钟信号是否导通或滞后输入信号的转换的电路。 发送电路包括串行电路，用于接收并行的一组位，并且响应于第一时钟信号而将该组比特顺序地输出到输出驱动器。 选择电路根据发送数据速率选择信号选择出站数据值内的数据位，以形成在串行化电路内接收的并行的一组位。 当发送数据速率选择信号处于第一状态时，选择出站数据值内的比特以实现第一数据速率，并且当发送数据速率选择信号处于第二状态时获得第二数据速率。

公开(公告)号：US20060250160A1

公开(公告)日：2006-11-09

申请号：US11456332

申请日：2006-07-10

申请人： Kun-Yung Chang ,  Mark Horowitz

发明人： Kun-Yung Chang ,  Mark Horowitz

IPC分类号： G01R13/00 ,  H03K19/00 ,  G01R29/26 ,  H01L25/00

CPC分类号： G06F1/06

摘要： A fault-tolerant clock generation circuit. First and second clock signal generators are provided to generate first and second clock signals. The second clock signal generator includes a locked loop circuit that, in a first operating mode, adjusts the phase of the second clock signal as necessary to maintain phase alignment between the first and second clock signals. A fail detect circuit is provided to determine whether a failure relating to generation of the first clock signal has occurred and, if so, to assert a hold signal. The locked loop circuit responds to assertion of the hold signal by transitioning to a second operating mode in which the phase of the second clock signal is not adjusted.

摘要翻译： 一个容错时钟发生电路。 提供第一和第二时钟信号发生器以产生第一和第二时钟信号。 第二时钟信号发生器包括锁定环路电路，其在第一操作模式中根据需要调整第二时钟信号的相位，以维持第一和第二时钟信号之间的相位对准。 提供故障检测电路以确定是否发生了与第一时钟信号的产生有关的故障，并且如果是，则断言保持信号。 锁定环电路通过转换到第二时钟信号的相位未被调整的第二操作模式来响应保持信号的断言。

公开(公告)号：US20060031698A1

公开(公告)日：2006-02-09

申请号：US11243032

申请日：2005-10-04

申请人： Scott Best ,  Abhijit Abhyankar ,  Kun-Yung Chang ,  Frank Lambrecht

发明人： Scott Best ,  Abhijit Abhyankar ,  Kun-Yung Chang ,  Frank Lambrecht

IPC分类号： G06F1/12

CPC分类号： G06F1/08 ,  G06F1/12 ,  G11C29/02 ,  G11C29/022 ,  G11C29/028 ,  G11C29/50012 ,  H04L7/0004 ,  H04L7/0008 ,  H04L7/0033 ,  H04L7/0091 ,  H04L7/033 ,  H04L7/10 ,  H04L25/14

摘要： A communication channel includes a first component having a transmitter coupled to a normal signal source, and a second component having a receiver coupled to a normal signal destination. A communication link couples the first and second components. Calibration logic provides for setting an operation value for a parameter of the communication channel, such as by executing an exhaustive calibration sequence at initialization of the link. A tracking circuit, including a monitoring function, tracks drift in the parameter by monitoring a feedback signal that has a characteristic that correlates with drift in the communication channel, and updates, or indicates the need for updating of, the operation value of the parameter in response to the monitoring function.

公开(公告)号：US20050068073A1

公开(公告)日：2005-03-31

申请号：US10770435

申请日：2004-02-03

申请人： Xudong Shi ,  Kun-Yung Chang

发明人： Xudong Shi ,  Kun-Yung Chang

IPC分类号： H03L7/081 ,  H03L7/089 ,  H03L7/093 ,  H03L7/107 ,  H03L7/06

CPC分类号： H03L7/093 ,  H03L7/0812 ,  H03L7/0893 ,  H03L7/107

摘要： A PLL/DLL circuit is current self-biased responsive to a current Ild provided from a voltage regulator to a VCO or VCDL. Bias current Ibias, which is proportional to Ild, is provided to components of the PLL/DLL, such as a charge pump or loop resistor, from an interconnect coupled to the voltage regulator. In an embodiment of the present invention, a component of the PLL/DLL includes a bias-generating device, such as a MOSFET p-type transistor having a drain coupled to the interconnect. In an embodiment of the present invention, a voltage regulator includes an AMP having a bias-generating device, such as a p-type transistor, acting as a current source, having a source coupled to Vdd and a drain coupled to the interconnect. The gate of the bias-generating device is coupled to the gate of four other p-type devices. Each of the four p-type devices has a source coupled to Vdd. The drains of the first and second p-type transistors are coupled to an output providing Ild. A negative input of the AMP (“INM”) is coupled to the gate of a first n-type transistor and a positive input of the AMP (“INP”) is coupled to the gate of a second n-type transistor. The drains of the first and second n-type transistors are coupled to the drains of the second and third p-type transistors. The sources of the first and second n-type transistors are coupled to the drain of a third n-type transistor. The source of the third n-type transistor is coupled to ground and the gate is coupled to a fourth n-type transistor. The drain of the fourth n-type transistor is coupled to the drain of the fourth p-type transistor and the source of the fourth n-type transistor is coupled to ground.

摘要翻译： 响应于从电压调节器提供给VCO或VCDL的电流Ild，PLL / DLL电路是电流自偏置的。 与Ild成比例的偏置电流Ibias从耦合到电压调节器的互连器件提供给PLL / DLL的组件，例如电荷泵或环路电阻器。 在本发明的一个实施例中，PLL / DLL的组件包括偏置产生装置，例如具有耦合到互连的漏极的MOSFET p型晶体管。 在本发明的一个实施例中，电压调节器包括具有偏置产生装置的AMP，例如用作电流源的p型晶体管，其具有耦合到Vdd的源极和耦合到互连的漏极。 偏置产生装置的栅极耦合到四个其它p型装置的栅极。 四个p型设备中的每一个具有耦合到Vdd的源。 第一和第二p型晶体管的漏极耦合到提供Ild的输出。 AMP（“INM”）的负输入耦合到第一n型晶体管的栅极，并且AMP（“INP”）的正输入端耦合到第二n型晶体管的栅极。 第一和第二n型晶体管的漏极耦合到第二和第三p型晶体管的漏极。 第一和第二n型晶体管的源极耦合到第三n型晶体管的漏极。 第三n型晶体管的源极耦合到地，并且栅极耦合到第四n型晶体管。 第四n型晶体管的漏极耦合到第四p型晶体管的漏极，第四n型晶体管的源极耦合到地。