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    DRIFT TRACKING FEEDBACK FOR COMMUNICATION CHANNELS
    1.
    发明申请
    DRIFT TRACKING FEEDBACK FOR COMMUNICATION CHANNELS 有权
    用于通信信道的跟踪跟踪反馈

    公开(公告)号：US20070204184A1

    公开(公告)日：2007-08-30

    申请号：US11744006

    申请日：2007-05-03

    申请人： Scott Best ,  Abhijit Abhyankar ,  Kun-Yung Chang ,  Frank Lambrecht

    发明人： Scott Best ,  Abhijit Abhyankar ,  Kun-Yung Chang ,  Frank Lambrecht

    IPC分类号： G06F1/12

    CPC分类号： G06F1/08 ,  G06F1/12 ,  G11C29/02 ,  G11C29/022 ,  G11C29/028 ,  G11C29/50012 ,  H04L7/0004 ,  H04L7/0008 ,  H04L7/0033 ,  H04L7/0091 ,  H04L7/033 ,  H04L7/10 ,  H04L25/14

    摘要： A communication channel includes a first component having a transmitter coupled to a normal signal source, and a second component having a receiver coupled to a normal signal destination. A communication link couples the first and second components. Calibration logic provides for setting an operation value for a parameter of the communication channel, such as by executing an exhaustive calibration sequence at initialization of the link. A tracking circuit, including a monitoring function, tracks drift in the parameter by monitoring a feedback signal that has a characteristic that correlates with drift in the communication channel, and updates, or indicates the need for updating of, the operation value of the parameter in response to the monitoring function.

    摘要翻译： 通信信道包括具有耦合到正常信号源的发射机的第一分量和具有耦合到正常信号目的地的接收机的第二分量。 通信链路耦合第一和第二组件。 校准逻辑提供了设置通信信道参数的操作值，例如通过在链路初始化时执行穷举校准序列。 包括监视功能的跟踪电路通过监视具有与通信信道中的漂移相关的特征的反馈信号来跟踪参数中的漂移，并且更新或指示更新参数的操作值的需要 响应监控功能。

    DRIFT TRACKING FEEDBACK FOR COMMUNICATION CHANNELS
    3.
    发明申请
    DRIFT TRACKING FEEDBACK FOR COMMUNICATION CHANNELS 有权
    用于通信信道的跟踪跟踪反馈

    公开(公告)号：US20050210308A1

    公开(公告)日：2005-09-22

    申请号：US10802634

    申请日：2004-03-17

    申请人： Scott Best ,  Abhijit Abhyankar ,  Kun-Yung Chang ,  Frank Lambrecht

    发明人： Scott Best ,  Abhijit Abhyankar ,  Kun-Yung Chang ,  Frank Lambrecht

    IPC分类号： G06F1/04 ,  H04L7/00 ,  H04L7/10 ,  H04L25/14

    CPC分类号： G06F1/08 ,  G06F1/12 ,  G11C29/02 ,  G11C29/022 ,  G11C29/028 ,  G11C29/50012 ,  H04L7/0004 ,  H04L7/0008 ,  H04L7/0033 ,  H04L7/0091 ,  H04L7/033 ,  H04L7/10 ,  H04L25/14

    摘要： A communication channel includes a first component having a transmitter coupled to a normal signal source, and a second component having a receiver coupled to a normal signal destination. A communication link couples the first and second components. Calibration logic provides for setting an operation value for a parameter of the communication channel, such as by executing an exhaustive calibration sequence at initialization of the link. A tracking circuit, including a monitoring function, tracks drift in the parameter by monitoring a feedback signal that has a characteristic that correlates with drift in the communication channel, and updates, or indicates the need for updating of, the operation value of the parameter in response to the monitoring function.

    摘要翻译： 通信信道包括具有耦合到正常信号源的发射机的第一分量和具有耦合到正常信号目的地的接收机的第二分量。 通信链路耦合第一和第二组件。 校准逻辑提供了设置通信信道参数的操作值，例如通过在链路初始化时执行穷举校准序列。 包括监视功能的跟踪电路通过监视具有与通信信道中的漂移相关的特征的反馈信号来跟踪参数中的漂移，并且更新或指示更新参数的操作值的需要 响应监控功能。

    Drift Tracking Feedback for Communication Channels
    4.
    发明申请
    Drift Tracking Feedback for Communication Channels 有权
    通信通道的漂移跟踪反馈

    公开(公告)号：US20070088968A1

    公开(公告)日：2007-04-19

    申请号：US11560031

    申请日：2006-11-15

    申请人： Scott Best ,  Abhijit Abhyankar ,  Kun Chang ,  Frank Lambrecht

    发明人： Scott Best ,  Abhijit Abhyankar ,  Kun Chang ,  Frank Lambrecht

    IPC分类号： G06F1/12

    CPC分类号： G06F1/08 ,  G06F1/12 ,  G11C29/02 ,  G11C29/022 ,  G11C29/028 ,  G11C29/50012 ,  H04L7/0004 ,  H04L7/0008 ,  H04L7/0033 ,  H04L7/0091 ,  H04L7/033 ,  H04L7/10 ,  H04L25/14

    摘要： A communication channel includes a first component having a transmitter coupled to a normal signal source, and a second component having a receiver coupled to a normal signal destination. A communication link couples the first and second components. Calibration logic provides for setting an operation value for a parameter of the communication channel, such as by executing an exhaustive calibration sequence at initialization of the link. A tracking circuit, including a monitoring function, tracks drift in the parameter by monitoring a feedback signal that has a characteristic that correlates with drift in the communication channel, and updates, or indicates the need for updating of, the operation value of the parameter in response to the monitoring function.

    摘要翻译： 通信信道包括具有耦合到正常信号源的发射机的第一分量和具有耦合到正常信号目的地的接收机的第二分量。 通信链路耦合第一和第二组件。 校准逻辑提供了设置通信信道参数的操作值，例如通过在链路初始化时执行穷举校准序列。 包括监视功能的跟踪电路通过监视具有与通信信道中的漂移相关的特征的反馈信号来跟踪参数中的漂移，并且更新或指示更新参数的操作值的需要 响应监控功能。

    Memory components and controllers that calibrate multiphase synchronous timing references
    5.
    发明授权
    Memory components and controllers that calibrate multiphase synchronous timing references 有权
    校准多相同步定时参考的存储器组件和控制器

    公开(公告)号：US09412428B2

    公开(公告)日：2016-08-09

    申请号：US14003722

    申请日：2012-03-21

    申请人： Thomas Giovannini ,  Scott Best ,  Lei Luo ,  Ian Shaeffer

    发明人： Thomas Giovannini ,  Scott Best ,  Lei Luo ,  Ian Shaeffer

    IPC分类号： G06F12/00 ,  G11C7/22 ,  G11C29/02

    CPC分类号： G11C7/222 ,  G11C7/227 ,  G11C29/023 ,  G11C29/028 ,  G11C29/50012 ,  G11C29/56

    摘要： A first timing reference signal and a second timing reference signal are sent to a memory device. The second timing reference signal has approximately a quadrature phase relationship with respect to the first timing reference signal. A plurality of serial data patterns are received from the memory device. The transitions of the first timing reference and the second timing reference determining when transitions occur between the bits of the plurality of data patterns. Timing indicators associated with when received transitions occur between the bits of the plurality of data patterns are received from the memory device. The timing indicators are each measured using a single sampler. Based on the timing indicators, a first duty cycle adjustment for the first timing reference signal, a second duty cycle adjustment for the second timing reference signal, and a quadrature phase adjustment are determined and applied.

    摘要翻译： 第一定时参考信号和第二定时参考信号被发送到存储器件。 第二定时参考信号相对于第一定时参考信号具有近似的正交相位关系。 从存储装置接收多个串行数据模式。 第一定时参考和第二定时参考的转换确定何时在多个数据模式的位之间发生转换。 当从存储器装置接收到多个数据模式的位之间发生接收转换时相关联的定时指示符。 时间指示器均使用单个采样器进行测量。 基于定时指示器，确定并应用第一定时参考信号的第一占空比调整，第二定时参考信号的第二占空比调整和正交相位调整。

    Method and apparatus for selectably providing single-ended and differential signaling with controllable impedance and transition time
    6.
    发明授权
    Method and apparatus for selectably providing single-ended and differential signaling with controllable impedance and transition time 有权
    用于可选择地提供具有可控阻抗和转换时间的单端和差分信号的方法和装置

    公开(公告)号：US07154302B2

    公开(公告)日：2006-12-26

    申请号：US10952921

    申请日：2004-09-30

    申请人： Scott Best ,  Chiping Yang

    发明人： Scott Best ,  Chiping Yang

    IPC分类号： H03K17/16

    CPC分类号： H04L25/0298 ,  G06F13/4072 ,  G06F13/4086 ,  H03K17/164 ,  H03K19/018585 ,  H04L25/0272 ,  H04L25/0278 ,  H04L25/028 ,  H04L25/085 ,  H04L25/45

    摘要： A method and apparatus for selectably providing single-ended and differential signaling with controllable impedance and transition time is provided. According to the method and apparatus, a differential signal can be transmitted over two wires or two single-ended signals can be transmitted over the two wires. According to the method and apparatus, termination may be selected among a single-reference termination, a center termination, or a high-impedance termination. Regardless of the type of termination selected, a capability for dynamic control of the termination impedance is provided. Moreover, an ability to change impedances of termination elements to maintain a desired termination impedance for both single-reference termination and center termination modes by shifting bits is provided. Also, a capability for dynamic control of transition times of signals is provided.

    摘要翻译： 提供了一种可选择地提供具有可控阻抗和转换时间的单端和差分信号的方法和装置。 根据该方法和装置，差分信号可以通过两条线路传输，或者两条单端信号可以通过两条线路传输。 根据该方法和装置，可以在单参考终端，中心终端或高阻抗终端中选择终止。 不管选择的终端类型如何，都提供了终端阻抗的动态控制能力。 此外，提供了通过移位来改变端接元件的阻抗以维持单参考端接和中心端接模式的期望的终端阻抗的能力。 此外，还提供了用于动态控制信号的转换时间的能力。

    Advertising display assembly having a hinged support
    7.
    发明申请
    Advertising display assembly having a hinged support 审中-公开
    具有铰链支架的广告显示组件

    公开(公告)号：US20050156427A1

    公开(公告)日：2005-07-21

    申请号：US11033652

    申请日：2005-01-12

    申请人： Scott Best ,  James Turner

    发明人： Scott Best ,  James Turner

    IPC分类号： G09F1/06 ,  G09F1/14 ,  G09F1/00

    CPC分类号： G09F1/06 ,  G09F1/14

    摘要： The subject invention provides an advertising display assembly (10) including two layers of stock material (12, 28) defining a plurality of outer peripheral edges (42, 44, 46). A release liner (24) is sandwiched therebetween. A plurality of score lines (62) define an integral coupon card (20) within the assembly (10) and an outer strip of material (22) between the integral card (20) and the outer peripheral edges (42, 44, 46). A plurality of mini-coupons (58) are detachably cut into the integral card (20) through the second layer of stock material (28). The assembly (10) is characterized by a hinge (74) extending across the strip of material (22) and defining an upper portion (76) and a lower portion (78) in the strip of material (22). The lower portion (78) of the strip of material (22) rotates relative to the upper portion (76) and the integral card (20) for supporting the assembly (10) on a surface (80) in an upright position for display.

    摘要翻译： 本发明提供一种广告显示组件（10），其包括限定多个外围边缘（42,44,46）的两层原料（12,28）。 释放衬垫（24）夹在其间。 多个刻痕线（62）在组合件（10）内限定积分券（20）和整体卡（20）与外围边缘（42,44,46）之间的外部材料条（22） 。 通过第二层原料（28）将多个小型试样（58）可拆卸地切割成整体卡（20）。 组件（10）的特征在于延伸穿过材料条（22）并且限定材料条（22）中的上部（76）和下部（78）的铰链（74）。 材料条（22）的下部（78）相对于上部（76）和整体卡（20）旋转，用于将支架（10）支撑在直立位置的表面（80）上以进行显示。

    Circuit, apparatus and method for obtaining a lock state value
    8.
    发明申请
    Circuit, apparatus and method for obtaining a lock state value 失效
    用于获得锁定状态值的电路，装置和方法

    公开(公告)号：US20050035798A1

    公开(公告)日：2005-02-17

    申请号：US10638857

    申请日：2003-08-11

    申请人： Scott Best

    发明人： Scott Best

    IPC分类号： H03L7/06 ,  H03L7/089 ,  H03L7/095

    CPC分类号： H03L7/095 ,  H03L7/0891

    摘要： A circuit, apparatus and method provides a lock state value representing an amount of time a phase alignment circuit (“PAC”), such as a PLL or DLL, is tracking or locked to an incoming reference signal for a predetermined period of time. In an embodiment of the present invention, a lock state detection circuit is coupled to a lock loop circuit and includes a phase detection circuit and a counter circuit. The phase detection circuit includes a phase detector and delay elements that are coupled to the PAC phase detector. The phase detector outputs a lock state sample value of the PAC. In an embodiment of the present invention, the PAC is locked when a stream of alternating lock state sample values, logical 1's and 0's, are output from the phase detector. The counter circuit includes a flip-flop, an XOR gate and counter for obtaining a lock state value for a predetermined period of time.

    摘要翻译： 电路，装置和方法提供一个锁定状态值，表示在预定的时间段内相位对准电路（“PAC”）如PLL或DLL正在跟踪或锁定到输入参考信号的时间量。 在本发明的实施例中，锁定状态检测电路耦合到锁定环电路，并且包括相位检测电路和计数器电路。 相位检测电路包括耦合到PAC相位检测器的相位检测器和延迟元件。 相位检测器输出PAC的锁定状态采样值。 在本发明的实施例中，当从相位检测器输出交替锁定状态采样值逻辑1和0的流时，PAC被锁定。 计数器电路包括触发器，XOR门和用于在预定时间段内获得锁定状态值的计数器。

    Apparatus and method for a digital delay locked loop
    10.
    发明授权
    Apparatus and method for a digital delay locked loop 有权
    数字延迟锁定环的装置和方法

    公开(公告)号：US06642760B1

    公开(公告)日：2003-11-04

    申请号：US10112963

    申请日：2002-03-29

    申请人： Elad Alon ,  Scott Best

    发明人： Elad Alon ,  Scott Best

    IPC分类号： H03L706

    CPC分类号： H03K3/037 ,  H03K3/0375 ,  H03L7/0802 ,  H03L7/0814

    摘要： A circuit and method is shown for digital control of delay lines in a delay locked loop (DLL) system. A pair of multiplexors (MUXes) is used to select output taps from a pair of complementary delay lines that delay a reference clock signal in order to lock onto a received clock signal. An output tap from one delay line is used to produce a rising edge in an output clock signal while a corresponding tap in the complementary delay line is used to produce a falling edge in the output signal in order to correct for distortion. The MUXes are controlled based on a phase difference detected between the received clock signal and a feedback clock corresponding to the output clock signal. Another aspect of the present invention provides for generation of a quadrature clock by interpolating between the rising and falling edges selected for the output clock signal. Still another aspect of the present invention provides for selectively disabling unused elements of the delay lines to reduce power consumption.

    摘要翻译： 示出了延迟锁定环（DLL）系统中的延迟线的数字控制的电路和方法。 一对多路复用器（MUX）用于从延迟参考时钟信号的一对互补延迟线中选择输出抽头，以便锁定到所接收的时钟信号上。 来自一个延迟线的输出抽头用于产生输出时钟信号中的上升沿，而互补延迟线中的相应抽头用于在输出信号中产生下降沿以便校正失真。 基于在接收的时钟信号和对应于输出时钟信号的反馈时钟之间检测到的相位差来控制MUX。 本发明的另一方面提供了通过在为输出时钟信号选择的上升沿和下降沿之间进行内插来产生正交时钟。 本发明的另一方面提供了选择性地禁用延迟线的未使用元件以降低功耗。