公开(公告)号：US20070147569A1

公开(公告)日：2007-06-28

申请号：US11685017

申请日：2007-03-12

申请人： Kun-Yung Chang ,  Kevin Donnelly

发明人： Kun-Yung Chang ,  Kevin Donnelly

IPC分类号： H03D3/24

CPC分类号： H04L7/0337 ,  H03L7/07 ,  H03L7/0814 ,  H03L7/091 ,  H04L7/0025

摘要： An integrated circuit device having a selectable data rate clock data recovery (CDR) circuit and a selectable data rate transmit circuit. The CDR circuit includes a receive circuit to capture a plurality of samples of an input signal during a cycle of a first clock signal. A select circuit is coupled to the receive circuit to select, according to a receive data rate select signal, one of the plurality of samples to be a first selected sample of the input signal and another of the plurality of samples to be a second selected sample of the input signal. A phase control circuit is coupled to receive the first and second selected samples of the input signal and includes circuitry to compare the selected samples to determine whether the first clock signal leads or lags a transition of the input signal. The transmit circuit includes a serializing circuit to receive a parallel set of bits and to output the set of bits in sequence to an output driver in response to a first clock signal. A select circuit selects, according to a transmit data rate select signal, data bits within an outbound data value to form the parallel set of bits received within the serializing circuit. Bits within the outbound data value are selected to achieve a first data rate when the transmit data rate select signal is in a first state, and to achieve a second data rate when the transmit data rate select signal is in a second state.

摘要翻译： 一种具有可选数据速率时钟数据恢复（CDR）电路和可选数据速率发射电路的集成电路装置。 CDR电路包括在第一时钟信号的周期期间捕获输入信号的多个采样的接收电路。 选择电路耦合到接收电路，以根据接收数据速率选择信号选择多个采样中的一个作为输入信号的第一选定采样，并将多个样本中的另一个作为第二选定采样 的输入信号。 相位控制电路被耦合以接收输入信号的第一和第二选定采样，并且包括用于比较所选择的采样以确定第一时钟信号是否导通或滞后输入信号的转换的电路。 发送电路包括串行电路，用于接收并行的一组位，并且响应于第一时钟信号而将该组比特顺序地输出到输出驱动器。 选择电路根据发送数据速率选择信号选择出站数据值内的数据位，以形成在串行化电路内接收的并行的一组位。 当发送数据速率选择信号处于第一状态时，选择出站数据值内的比特以实现第一数据速率，并且当发送数据速率选择信号处于第二状态时获得第二数据速率。

公开(公告)号：US20120147944A1

公开(公告)日：2012-06-14

申请号：US13391383

申请日：2010-09-14

申请人： Amir Amirkhany ,  Chaofeng Huang ,  Kambiz Kaviani ,  Wayne D. Dettloof ,  Kun-Yung Chang

发明人： Amir Amirkhany ,  Chaofeng Huang ,  Kambiz Kaviani ,  Wayne D. Dettloof ,  Kun-Yung Chang

IPC分类号： H04L27/01

CPC分类号： H03K19/0005 ,  H03K19/017581 ,  H03M1/1061 ,  H03M1/745 ,  H04L25/0278 ,  H04L25/0288 ,  H04L25/03343

摘要： High resolution output drivers having a relatively small number of sub-driver branches or slices each having nominal impedances substantially larger than a quantization step and that incrementally differ from one another by an impedance step substantially smaller than a quantization step. In one implementation, such “differential” or “non-uniform” sub-driver slices implement respective elements of an n choose k equalizer, with each such differential sub-driver slice being implemented by a uniform-element impedance calibration DAC. In another implementation, each component of a uniform-slice equalizer is implemented by a differential-slice impedance calibration DAC, and in yet another implementation, each component of a differential-slice equalizer is implemented by a differential-slice impedance calibration DAC. In an additional set of implementations, equalization and impedance calibration functions are implemented bilaterally in respective parallel sets of driver branches, rather than in the nested “DAC within a DAC” arrangement of the hierarchical implementations. Through such bilateral arrangement, multiplication of the equalizer and calibrator quantizations is avoided, thereby lowering the total number of sub-driver slices required to meet the specified ranges and resolutions.

摘要翻译： 具有相对较少数量的子驱动器分支或切片的高分辨率输出驱动器，每个子驱动器分支或切片具有显着大于量化步长的标称阻抗，并且通过显着小于量化步长的阻抗步长递增地彼此不同。 在一个实现中，这种“差分”或“不均匀”子驱动器切片实现n选择k均衡器的相应元件，每个这样的差分子驱动器切片由均匀元件阻抗校准DAC实现。 在另一实施方式中，均匀分片均衡器的每个分量由差分片阻抗校准DAC实现，并且在又一实现中，差分片均衡器的每个分量由差分片阻抗校准DAC实现。 在一组额外的实施方案中，均衡和阻抗校准功能在各个并行的驱动器分支组中实现，而不是分层实现中嵌套的“DAC内的DAC”布置。 通过这种双边安排，避免了均衡器和校准器量化的乘法，从而降低了满足指定范围和分辨率所需的副驱动器片的总数。

公开(公告)号：US20120099678A1

公开(公告)日：2012-04-26

申请号：US13341612

申请日：2011-12-30

申请人： Kun-Yung Chang ,  Fariborz Assaderaghi

发明人： Kun-Yung Chang ,  Fariborz Assaderaghi

IPC分类号： H04L27/06 ,  H04L7/00

CPC分类号： H03L7/00 ,  H03L7/06

摘要： A circuit includes a frequency synthesizer, N phase mixers coupled to the frequency synthesizer, a plurality of receivers, and a calibration circuit. The frequency synthesizer is to receive a reference clock signal and is to output a primary clock signal. A respective phase mixer in the N phase mixers is to output a respective secondary clock signal having a corresponding phase. A respective receiver in the plurality of receivers is coupled to two of the N phase mixers, and at a respective time is to receive data in accordance with the respective secondary clock signal from one of the two phase mixers coupled to the respective receiver. The calibration circuit is to calibrate a secondary clock signal output by a respective phase mixer in the N phase mixers by adjusting the phase of the secondary clock signal of the respective phase mixer.

摘要翻译： 电路包括频率合成器，耦合到频率合成器的N相混频器，多个接收器和校准电路。 频率合成器是接收参考时钟信号，并输出主时钟信号。 N相混频器中的相应的混频器将输出具有相应相位的相应次级时钟信号。 多个接收机中的相应接收机耦合到N相混合器中的两个，并且在相应的时间是根据耦合到相应接收机的两个相位混合器之一的相应辅助时钟信号接收数据。 校准电路是通过调整相位相位混合器的次级时钟信号的相位来校准由N相混频器中的各个相位混频器输出的次级时钟信号。

公开(公告)号：US20120014427A1

公开(公告)日：2012-01-19

申请号：US13171363

申请日：2011-06-28

申请人： Kun-Yung Chang

发明人： Kun-Yung Chang

IPC分类号： H04B17/00 ,  H04L27/04

CPC分类号： H04L27/0014 ,  H04L2027/0053 ,  H04L2027/0067 ,  H04L2027/0095

摘要： An integrated circuit includes samplers, a phase error determination circuit, and periodic signal generators. The samplers generate respective sampled signals by sampling respective input signals in response to respective periodic signals. The input signals have a common phase error. The phase error determination circuit receives the sampled signals from the samplers. The phase error determination circuit generates a representation of the common phase error of the input signals in response to sampled signals received in a set-up mode in which the samplers sample respective input signals having a common bit pattern. The periodic signal generators generate the periodic signals differing in phase from one another by defined phase differences in the set-up mode and subject the periodic signals to a common phase shift in a normal mode in response to the representation of the common phase error. The common phase shift matches the common phase error of the input signals.

摘要翻译： 集成电路包括采样器，相位误差确定电路和周期信号发生器。 采样器通过响应于各个周期信号对相应的输入信号进行采样来产生相应的采样信号。 输入信号具有共同的相位误差。 相位误差判定电路从采样器接收采样信号。 相位误差确定电路响应于在采样器采样具有公共位模式的各个输入信号的建立模式中接收的采样信号，生成输入信号的公共相位误差的表示。 周期性信号发生器通过设定模式中的相位差产生相位不同的周期信号，并且响应于公共相位误差的表示，将周期信号在正常模式中进行公共相移。 公共相移匹配输入信号的公共相位误差。

公开(公告)号：US20070204184A1

公开(公告)日：2007-08-30

申请号：US11744006

申请日：2007-05-03

申请人： Scott Best ,  Abhijit Abhyankar ,  Kun-Yung Chang ,  Frank Lambrecht

发明人： Scott Best ,  Abhijit Abhyankar ,  Kun-Yung Chang ,  Frank Lambrecht

IPC分类号： G06F1/12

CPC分类号： G06F1/08 ,  G06F1/12 ,  G11C29/02 ,  G11C29/022 ,  G11C29/028 ,  G11C29/50012 ,  H04L7/0004 ,  H04L7/0008 ,  H04L7/0033 ,  H04L7/0091 ,  H04L7/033 ,  H04L7/10 ,  H04L25/14

摘要： A communication channel includes a first component having a transmitter coupled to a normal signal source, and a second component having a receiver coupled to a normal signal destination. A communication link couples the first and second components. Calibration logic provides for setting an operation value for a parameter of the communication channel, such as by executing an exhaustive calibration sequence at initialization of the link. A tracking circuit, including a monitoring function, tracks drift in the parameter by monitoring a feedback signal that has a characteristic that correlates with drift in the communication channel, and updates, or indicates the need for updating of, the operation value of the parameter in response to the monitoring function.

摘要翻译： 通信信道包括具有耦合到正常信号源的发射机的第一分量和具有耦合到正常信号目的地的接收机的第二分量。 通信链路耦合第一和第二组件。 校准逻辑提供了设置通信信道参数的操作值，例如通过在链路初始化时执行穷举校准序列。 包括监视功能的跟踪电路通过监视具有与通信信道中的漂移相关的特征的反馈信号来跟踪参数中的漂移，并且更新或指示更新参数的操作值的需要 响应监控功能。

公开(公告)号：US07839194B2

公开(公告)日：2010-11-23

申请号：US12256422

申请日：2008-10-22

申请人： Kun-Yung Chang ,  Ting Wu

发明人： Kun-Yung Chang ,  Ting Wu

IPC分类号： H03K3/017

CPC分类号： H03K5/1565 ,  G06F1/06 ,  G06F1/12

摘要： Clocking circuitry includes a first clock generator to generate a first clock signal and having a first duty cycle correction input, and a second clock generator to generate a second clock signal and having a second duty cycle correction input. Some embodiments have more than two clock generators. A multiplexer selects between the clock signals from the clock generators. The multiplexer has a first input coupled to the first clock signal and has a second input coupled to the second clock signal, and has a clock output coupled to a clock input of a duty cycle circuit. The duty cycle circuit receives the selected clock signal from the multiplexer and generates a duty cycle correction signal.

摘要翻译： 时钟电路包括用于产生第一时钟信号并具有第一占空比校正输入的第一时钟发生器，以及产生第二时钟信号并具有第二占空比校正输入的第二时钟发生器。 一些实施例具有两个以上的时钟发生器。 多路复用器在来自时钟发生器的时钟信号之间进行选择。 所述多路复用器具有耦合到所述第一时钟信号的第一输入端，并且具有耦合到所述第二时钟信号的第二输入，并且具有耦合到占空比电路的时钟输入的时钟输出。 占空比电路从多路复用器接收所选择的时钟信号，并产生占空比校正信号。

公开(公告)号：US20090031091A1

公开(公告)日：2009-01-29

申请号：US12137935

申请日：2008-06-12

申请人： Kun-Yung Chang ,  Fariborz Assaderaghi ,  Hae-Chang Lee

发明人： Kun-Yung Chang ,  Fariborz Assaderaghi ,  Hae-Chang Lee

IPC分类号： G06F12/00

CPC分类号： G06F13/1689

摘要： A system that adjusts the timing of write operations at a memory controller is described. This system operates by observing timing drift for read data at the memory controller, and then adjusting the timing of write operations at the memory controller based on the observed timing drift for the read data.

摘要翻译： 描述了调整存储器控制器上的写入操作的定时的系统。 该系统通过观察存储器控制器上的读取数据的定时漂移，然后基于观察到的读取数据的定时漂移来调整存储器控制器上的写入操作的定时。

公开(公告)号：US07365581B2

公开(公告)日：2008-04-29

申请号：US11743422

申请日：2007-05-02

申请人： Xudong Shi ,  Kun-Yung Chang

发明人： Xudong Shi ,  Kun-Yung Chang

IPC分类号： H03L7/06

CPC分类号： H03L7/093 ,  H03L7/0812 ,  H03L7/0893 ,  H03L7/107

摘要： A PLL/DLL circuit is current self-biased responsive to a current Ild provided from a voltage regulator to a VCO or VCDL. Bias current Ibias, which is proportional to Ild, is provided to components of the PLL/DLL, such as a charge pump or loop resistor, from an interconnect coupled to the voltage regulator. In an embodiment of the present invention, a component of the PLL/DLL includes a bias-generating device, such as a MOSFET p-type transistor having a drain coupled to the interconnect. In an embodiment of the present invention, a voltage regulator includes an AMP having a bias-generating device, such as a p-type transistor, acting as a current source, having a source coupled to Vdd and a drain coupled to the interconnect. The gate of the bias-generating device is coupled to the gate of four other p-type devices. Each of the four p-type devices has a source coupled to Vdd. The drains of the first and second p-type transistors are coupled to an output providing Ild. A negative input of the AMP (“INM”) is coupled to the gate of a first n-type transistor and a positive input of the AMP (“INP”) is coupled to the gate of a second n-type transistor. The drains of the first and second n-type transistors are coupled to the drains of the second and third p-type transistors. The sources of the first and second n-type transistors are coupled to the drain of a third n-type transistor. The source of the third n-type transistor is coupled to ground and the gate is coupled to a fourth n-type transistor. The drain of the fourth n-type transistor is coupled to the drain of the fourth p-type transistor and the source of the fourth n-type transistor is coupled to ground.

摘要翻译： 响应于从电压调节器提供给VCO或VCDL的电流I OUT，PLL / DLL电路是电流自偏置的。 与I / O成正比的偏置电流I SUB偏置被提供给PLL / DLL的组件，例如电荷泵或回路电阻器，其耦合到 电压调节器。 在本发明的一个实施例中，PLL / DLL的组件包括偏置产生装置，例如具有耦合到互连的漏极的MOSFET p型晶体管。 在本发明的一个实施例中，电压调节器包括AMP，其具有偏置产生装置，例如用作电流源的p型晶体管，其具有耦合到Vdd的源极和 漏极耦合到互连。 偏置产生装置的栅极耦合到四个其它p型装置的栅极。 四个p型器件中的每一个具有耦合到Vdd的源极。 第一和第二p型晶体管的漏极耦合到提供I / D的输出。 AMP（“INM”）的负输入耦合到第一n型晶体管的栅极，并且AMP（“INP”）的正输入端耦合到第二n型晶体管的栅极。 第一和第二n型晶体管的漏极耦合到第二和第三p型晶体管的漏极。 第一和第二n型晶体管的源极耦合到第三n型晶体管的漏极。 第三n型晶体管的源极耦合到地，并且栅极耦合到第四n型晶体管。 第四n型晶体管的漏极耦合到第四p型晶体管的漏极，第四n型晶体管的源极耦合到地。

公开(公告)号：US06961862B2

公开(公告)日：2005-11-01

申请号：US10802634

申请日：2004-03-17

申请人： Scott C. Best ,  Abhijit M. Abhyankar ,  Kun-Yung Chang ,  Frank Lambrecht

发明人： Scott C. Best ,  Abhijit M. Abhyankar ,  Kun-Yung Chang ,  Frank Lambrecht

IPC分类号： G06F1/04 ,  H04L7/00 ,  H04L7/10 ,  H04L25/14

CPC分类号： G06F1/08 ,  G06F1/12 ,  G11C29/02 ,  G11C29/022 ,  G11C29/028 ,  G11C29/50012 ,  H04L7/0004 ,  H04L7/0008 ,  H04L7/0033 ,  H04L7/0091 ,  H04L7/033 ,  H04L7/10 ,  H04L25/14

摘要： A communication channel includes a first component having a transmitter coupled to a normal signal source, and a second component having a receiver coupled to a normal signal destination. A communication link couples the first and second components. Calibration logic provides for setting an operation value for a parameter of the communication channel, such as by executing an exhaustive calibration sequence at initialization of the link. A tracking circuit, including a monitoring function, tracks drift in the parameter by monitoring a feedback signal that has a characteristic that correlates with drift in the communication channel, and updates, or indicates the need for updating of, the operation value of the parameter in response to the monitoring function.

摘要翻译： 通信信道包括具有耦合到正常信号源的发射机的第一分量和具有耦合到正常信号目的地的接收机的第二分量。 通信链路耦合第一和第二组件。 校准逻辑提供了设置通信信道参数的操作值，例如通过在链路初始化时执行穷举校准序列。 包括监视功能的跟踪电路通过监视具有与通信信道中的漂移相关的特征的反馈信号来跟踪参数中的漂移，并且更新或指示更新参数的操作值的需要 响应监控功能。

公开(公告)号：US08942319B2

公开(公告)日：2015-01-27

申请号：US13072642

申请日：2011-03-25

申请人： Chintan S. Thakkar ,  Kun-Yung Chang ,  Ting Wu

发明人： Chintan S. Thakkar ,  Kun-Yung Chang ,  Ting Wu

IPC分类号： H03D3/22 ,  H04L27/22 ,  H04L25/03

CPC分类号： H04L25/03057 ,  H04L7/0045 ,  H04L7/0058 ,  H04L7/0087 ,  H04L25/03063 ,  H04L2025/03369

摘要： A multi-phase partial response receiver supports various incoming data rates by sampling PrDFE output values at a selected one of at least two clock phases. The receiver includes a calibration circuit that performs a timing analysis of critical data paths in the circuit, and this analysis is then used to select the particular clock phase used to latch the output values. These techniques permit the multiplexer outputs from for each phase of the partial response receiver to directly drive selection of a multiplexer for the ensuing phase, i.e., by avoiding regions of instability or uncertainty in the respective multiplexer outputs.