公开(公告)号：US20140346563A1

公开(公告)日：2014-11-27

申请号：US13902729

申请日：2013-05-24

Applicant: ANALOG DEVICES, INC.

Inventor： Javier Alejandro Salcedo ,  Karl Sweetland

IPC: H01L27/02

CPC classification number: H01L27/0262 ,  H01L29/7436

Abstract: The disclosed technology relates to an apparatus for protection against transient electrical events. In one aspect, the apparatus includes an analog switch with high bipolar blocking voltage comprising a first p-type well region, a second p-type well region, a first n-type well region disposed between the first and second p-type well regions, and a deep n-type well region surrounding the first p-type well region, the second p-type well region, and the first n-type well region. The apparatus additionally includes a first native n-type region disposed between the first p-type well region the n-type well region and a second native n-type region disposed between the second p-type well region and n-type well region. The apparatus is configured such that the first p-type well region serves as an emitter/collector of a bidirectional PNP bipolar transistor. In addition, the apparatus is configured such that the first native n-type region, the first n-type well region, and the second native n-type region serves as a base of the bidirectional PNP bipolar transistor. Furthermore, the apparatus is configured such that the second p-type well region is configured as a collector/emitter of the bidirectional PNP bipolar transistor.

Abstract translation: 所公开的技术涉及用于防止瞬时电气事件的装置。 一方面，该装置包括具有高双极性阻断电压的模拟开关，包括第一p型阱区，第二p型阱区，设置在第一和第二p型阱区之间的第一n型阱区 以及围绕第一p型阱区域，第二p型阱区域和第一n型阱区域的深n型阱区域。 该装置还包括设置在第一p型阱区n型阱区和设置在第二p型阱区与n型阱区之间的第二天然n型区之间的第一天然n型区。 该装置被配置为使得第一p型阱区域用作双向PNP双极晶体管的发射极/集电极。 此外，该装置被配置为使得第一天然n型区域，第一n型阱区域和第二天然n型区域用作双向PNP双极晶体管的基极。 此外，该装置被配置为使得第二p型阱区被配置为双向PNP双极晶体管的集电极/发射极。

公开(公告)号：US08878344B2

公开(公告)日：2014-11-04

申请号：US13655026

申请日：2012-10-18

Applicant: Analog Devices, Inc.

Inventor： Srivatsan Parthasarathy ,  Javier Alejandro Salcedo ,  Shuyun Zhang

IPC: H01L29/66

CPC classification number: H01L29/735 ,  H01L29/20 ,  H01L29/6631

Abstract: Compound semiconductor lateral PNP bipolar transistors are fabricated based on processes traditionally used for formation of compound semiconductor NPN heterojunction bipolar transistors and hence such PNP bipolar transistors can be fabricated inexpensively using existing fabrication technologies. In particular, GaAs-based lateral PNP bipolar transistors are fabricated using GaAs-based NPN heterojunction bipolar transistor fabrication processes.

Abstract translation: 基于传统上用于形成化合物半导体NPN异质结双极晶体管的工艺制造复合半导体横向PNP双极晶体管，因此可以使用现有的制造技术廉价地制造这种PNP双极晶体管。 特别地，基于GaAs的NPN异质结双极晶体管制造工艺制造了基于GaAs的横向PNP双极晶体管。

公开(公告)号：US20140167106A1

公开(公告)日：2014-06-19

申请号：US13757588

申请日：2013-02-01

Applicant: ANALOG DEVICES, INC.

Inventor： Javier Alejandro Salcedo

IPC: H01L27/092

CPC classification number: H01L29/66378 ,  H01L27/0255 ,  H01L27/0262 ,  H01L27/092 ,  H01L29/0692 ,  H01L29/735 ,  H01L29/78 ,  H01L29/861

Abstract: Protection circuit architectures with integrated supply clamps and methods of forming the same are provided herein. In certain implementation, an integrated circuit interface protection device includes a first diode protection structure and a first thyristor protection structure electrically connected in parallel between a signal pin a power high supply. Additionally, the protection device includes a second diode protection structure and a second thyristor protection structure electrically connected in parallel between the signal pin and a power low supply. Furthermore, the protection device includes a third diode protection structure and a third thyristor protection structure electrically connected in parallel between the power high supply and the power low supply. The third thyristor protection structure and the third diode protection structure are synthesized as part of the integrated circuit interface and can share at least a portion of the wells and/or diffusion regions associated with the first and second thyristor protection structures.

公开(公告)号：US20140084331A1

公开(公告)日：2014-03-27

申请号：US13625611

申请日：2012-09-24

Applicant: ANALOG DEVICES, INC.

Inventor： Srivatsan Parthasarathy ,  Javier Alejandro Salcedo ,  Shuyun Zhang

IPC: H01L29/747 ,  H01L21/332

CPC classification number: H01L21/8252 ,  H01L27/0248 ,  H01L27/0605 ,  H01L29/41758 ,  H01L29/42316 ,  H01L29/7783

Abstract: A protection clamp is provided between a first terminal and a second terminal, and includes a multi-gate high electron mobility transistor (HEMT), a current limiting circuit, and a forward trigger control circuit. The multi-gate HEMT includes a drain/source, a source/drain, a first depletion-mode (D-mode) gate, a second D-mode gate, and an enhancement-mode (E-mode) gate disposed between the first and second D-mode gates. The drain/source and the first D-mode gate are connected to the first terminal and the source/drain and the second D-mode gate are connected to the second terminal. The forward trigger control and the current limiting circuits are coupled between the E-mode gate and the first and second terminals, respectively. The forward trigger control circuit provides an activation voltage to the E-mode gate when a voltage of the first terminal exceeds a voltage of the second terminal by a forward trigger voltage.

Abstract translation: 在第一端子和第二端子之间提供保护夹，并且包括多门高电子迁移率晶体管（HEMT），限流电路和正向触发控制电路。 多栅极HEMT包括漏极/源极，源极/漏极，第一耗尽模式（D模式）栅极，第二D模式栅极和设置在第一和第二栅极之间的增强模式（E模式）栅极 和第二D模式门。 漏极/源极和第一D型栅极连接到第一端子，源极/漏极和第二D型栅极连接到第二端子。 正向触发控制和限流电路分别耦合在E模式门和第一和第二端子之间。 当第一端子的电压通过正向触发电压超过第二端子的电压时，正向触发控制电路向E模式栅极提供激活电压。

公开(公告)号：US20200343721A1

公开(公告)日：2020-10-29

申请号：US16946917

申请日：2020-07-10

Applicant: Analog Devices, Inc.

Inventor： Srivatsan Parthasarathy ,  Javier Alejandro Salcedo ,  James Zhao

IPC: H02H9/04 ,  H02H9/00 ,  H01L27/02

Abstract: High voltage clamps with transient activation and activation release control are provided herein. In certain configurations, an integrated circuit (IC) includes a clamp electrically connected between a first node and a second node and having a control input. The IC further includes a first resistor-capacitor (RC) circuit that activates a detection signal in response to detecting a transient overstress event between the first node and the second node, an active feedback circuit that provides feedback from the first node to the control input of the clamp in response to activation of the detection signal, a second RC circuit that activates a shutdown signal after detecting passage of the transient overstress event based on low pass filtering a voltage difference between the first node and the second node, and a clamp shutdown circuit that turns off the clamp via the control input in response to activation of the shutdown signal.

公开(公告)号：US10734806B2

公开(公告)日：2020-08-04

申请号：US15215938

申请日：2016-07-21

Applicant: ANALOG DEVICES, INC.

Inventor： James Zhao ,  Javier Alejandro Salcedo ,  Srivatsan Parthasarathy

IPC: H02H9/04 ,  H02H9/00 ,  H01L27/02

Abstract: High voltage clamps with active activation and activation-release control are provided herein. In certain configurations, a clamp can have scalable operating clamping voltage level and can be used to protect the electrical circuit connected to a power supply of a semiconductor chip from damage from an overstress event, such as electrostatic discharge (ESD) events. The pins of the power supply are actively monitored to detect when an overstress event is present, and the clamp is turned-on in response to detecting the overstress event. A timer is used to shut down the clamp after a time delay from detecting the overstress event, thereby providing a false detection shutdown mechanism that prevents the protection clamp from getting falsely activated and remain in the on-state during normal circuit operation.

公开(公告)号：US10700056B2

公开(公告)日：2020-06-30

申请号：US16125319

申请日：2018-09-07

Applicant: ANALOG DEVICES, INC.

Inventor： James Zhao ,  Javier Alejandro Salcedo ,  Srivatsan Parthasarathy

IPC: H01L27/02 ,  H01L29/417 ,  H01L27/06 ,  H01L29/08 ,  H01L29/06 ,  H01L29/74 ,  H02H9/04 ,  B60R16/023

Abstract: A communication interface protection device includes a first electrical overstress (EOS) protection switch electrically connected to a first terminal and a second EOS protection switch electrically connected to a second terminal. Each of the first and second EOS protection switches includes a first semiconductor-controlled rectifier (SCR) and a second SCR and a first diode having a cathode electrically connected to an anode of the first SCR and a second diode having a cathode electrically connected to an anode of the second SCR. The first EOS protection device is configured to be activated in response to an EOS condition that causes a first bias between the first and second terminals, and wherein the second EOS protection device is configured to be activated in response to an EOS condition that causes a second bias between the first and second terminals.

公开(公告)号：US20200083212A1

公开(公告)日：2020-03-12

申请号：US16125319

申请日：2018-09-07

Applicant: ANALOG DEVICES, INC.

Inventor： James Zhao ,  Javier Alejandro Salcedo ,  Srivatsan Parthasarathy

IPC: H01L27/02 ,  H02H9/04 ,  H01L29/74 ,  H01L29/08 ,  H01L29/417 ,  H01L29/06 ,  H01L27/06 ,  B60R16/023

Abstract: A communication interface protection device includes a first electrical overstress (EOS) protection switch electrically connected to a first terminal and a second EOS protection switch electrically connected to a second terminal. Each of the first and second EOS protection switches includes a first semiconductor-controlled rectifier (SCR) and a second SCR and a first diode having a cathode electrically connected to an anode of the first SCR and a second diode having a cathode electrically connected to an anode of the second SCR. The first EOS protection device is configured to be activated in response to an EOS condition that causes a first bias between the first and second terminals, and wherein the second EOS protection device is configured to be activated in response to an EOS condition that causes a second bias between the first and second terminals.

公开(公告)号：US10404059B2

公开(公告)日：2019-09-03

申请号：US15428535

申请日：2017-02-09

Applicant: ANALOG DEVICES, INC.

Inventor： Javier Alejandro Salcedo ,  Srivatsan Parthasarathy ,  Linfeng He ,  Yuanzhong Zhou

IPC: H02H7/20 ,  H01L23/528 ,  H01L27/02 ,  H01L27/092

Abstract: Distributed switches to suppress transient electrical overstress-induced latch-up are provided. In certain configurations, an integrated circuit (IC) or semiconductor chip includes a transient electrical overstress detection circuit that activates a transient overstress detection signal in response to detecting a transient electrical overstress event between a pair of power rails. The IC further includes mixed-signal circuits and latch-up suppression switches distributed across the IC, and the latch-up suppression switches temporarily clamp the power rails to one another in response to activation of the transient overstress detection signal to inhibit latch-up of the mixed-signal circuits.

公开(公告)号：US20190051646A1

公开(公告)日：2019-02-14

申请号：US15674218

申请日：2017-08-10

Applicant: ANALOG DEVICES, INC.

Inventor： Javier Alejandro Salcedo ,  Linfeng He

IPC: H01L27/02 ,  H01L29/40

Abstract: An integrated circuit device for protecting circuits from transient electrical events is disclosed. An integrated circuit device includes a first bipolar junction transistor (BJT) and a second BJT cross-coupled with the first BJT to operate as a first semiconductor-controlled rectifier (SCR), where a base of the first BJT is connected to a collector of the second BJT, and a base of the second BJT is connected to an emitter or a collector of the first BJT. The integrated circuit device additionally includes a triggering device comprising a first diode having a cathode electrically connected to the base of the first BJT. The integrated circuit device further includes a third BJT cross-coupled with the second BJT to operate as a second SCR, where the third BJT has a collector connected to the base of the second BJT and a base connected to the collector of the second BJT.