公开(公告)号：US07733898B2

公开(公告)日：2010-06-08

申请号：US10924819

申请日：2004-08-25

申请人： Matthew Mattina ,  George Z. Chrysos ,  Yungho Choi

发明人： Matthew Mattina ,  George Z. Chrysos ,  Yungho Choi

IPC分类号： H04L12/43 ,  H04L1/00

CPC分类号： H04L12/43 ,  H04L47/10 ,  H04L47/11 ,  H04L47/13

摘要： A method and apparatus for preventing starvation in a slotted-ring network. Embodiments may include a ring interconnect to transmit bits, with one of the bits being a slot reservation bit, and nodes coupled to the ring interconnect, with each node comprising a starvation detection element and a slot reservation element to reserve a slot for future use. In further embodiments, each node may also comprise a slot tracking element to track the location of the slot reserved by that node.

摘要翻译： 一种用于防止开槽网络中的饥饿的方法和装置。 实施例可以包括用于传送比特的环形互连，其中一个比特是时隙保留比特，以及耦合到环形互连的节点，每个节点包括饥饿检测元素和时隙预留元素，以备将来使用的时隙。 在另外的实施例中，每个节点还可以包括跟踪由该节点保留的时隙的位置的时隙跟踪元件。

公开(公告)号：US07551564B2

公开(公告)日：2009-06-23

申请号：US10855355

申请日：2004-05-28

申请人： Matthew Mattina

发明人： Matthew Mattina

IPC分类号： G01R31/08

CPC分类号： H04L12/43 ,  H04L49/90

摘要： Embodiments of the present invention are related in general to data flow control in a network and in particular to packet flow control in a bidirectional ring interconnect. An embodiment of a method includes sending packets on the bidirectional ring interconnect in a first direction or on the bidirectional ring interconnect in a second direction, opposite to the first direction, between source and destination nodes on a semiconductor chip during a clock cycle based on a distance between the two nodes. An embodiment of an apparatus includes a semiconductor chip comprising a bidirectional ring interconnect and a plurality of nodes coupled to the bidirectional ring interconnect, where the bidirectional ring interconnect may transport packets in a clockwise or counterclockwise direction during a clock cycle based on the distance between source and destination nodes. Embodiments ensure single packet arrival at the destination node during any clock cycle. Exemplary applications include chip multiprocessing.

摘要翻译： 本发明的实施例一般涉及网络中的数据流控制，特别涉及双向环互连中的分组流控制。 一种方法的实施例包括在基于时钟周期的半导体芯片上的半导体芯片上的源和目的地节点之间沿与第一方向相反的第二方向的第一方向或双向环互连上的双向环形互连上的分组发送 两个节点之间的距离。 装置的实施例包括半导体芯片，其包括双向环互连和耦合到双向环互连的多个节点，其中双向环互连可以在时钟周期期间以顺时针或逆时针方向传输分组，基于源 和目标节点。 实施例确保在任何时钟周期期间单个分组到达目的地节点。 示例性应用包括芯片多处理。

公开(公告)号：US20050144390A1

公开(公告)日：2005-06-30

申请号：US10749752

申请日：2003-12-30

申请人： Matthew Mattina ,  George Chrysos

发明人： Matthew Mattina ,  George Chrysos

IPC分类号： G06F12/08 ,  G06F12/00

CPC分类号： G06F12/0813 ,  G06F12/0811 ,  G06F12/0831 ,  G06F12/084

摘要： The present application is a protocol for maintaining cache coherency in a CMP. The CMP design contains multiple processor cores with each core having it own private cache. In addition, the CMP has a single on-ship shared cache. The processor cores and the shared cache may be connected together with a synchronous, unbuffered bidirectional ring interconnect. In the present protocol, a single INVALIDATEANDACKNOWLEDGE message is sent on the ring to invalidate a particular core and acknowledge a particular core.

摘要翻译： 本申请是用于在CMP中维持高速缓存一致性的协议。 CMP设计包含多个处理器内核，每个内核都有自己的私有缓存。 此外，CMP具有单个在船共享缓存。 处理器核心和共享缓存可以与同步的，无缓冲的双向环互连连接在一起。 在本协议中，在环上发送单个INVALIDATEANDACKNOWLEDGE消息以使特定核心无效并且确认特定核心。

公开(公告)号：US09507745B1

公开(公告)日：2016-11-29

申请号：US14594299

申请日：2015-01-12

申请人： Ian Rudolf Bratt ,  Carl G. Ramey ,  Matthew Mattina

发明人： Ian Rudolf Bratt ,  Carl G. Ramey ,  Matthew Mattina

IPC分类号： G06F15/16 ,  G06F13/40 ,  G06F13/42

CPC分类号： G06F9/5022 ,  G06F9/4825 ,  G06F9/4881 ,  G06F9/544 ,  G06F11/1482 ,  G06F12/00 ,  G06F12/02 ,  G06F12/0806 ,  G06F12/0808 ,  G06F12/0844 ,  G06F12/0848 ,  G06F12/0864 ,  G06F12/0891 ,  G06F12/10 ,  G06F12/1027 ,  G06F12/12 ,  G06F12/121 ,  G06F12/123 ,  G06F13/4068 ,  G06F13/4221 ,  G06F15/16 ,  G06F15/8023 ,  G06F21/79 ,  G06F2212/502 ,  G06F2212/601 ,  H04L45/08 ,  H04L45/22 ,  H04L45/28 ,  H04L47/823 ,  H04L49/109

摘要： Communicating among cores in a computing system comprising a plurality of cores, each core comprising a processor and a switch, includes: routing a packet from a core or from a device coupled to at least one core to a destination over a route including one or more cores, with an order of dimensions associated with the route being selected dynamically upon construction of the packet; routing the packet to a first core in the route over the first selected dimension; and routing the packet from the first core to the destination over the second dimension.

公开(公告)号：US08572353B1

公开(公告)日：2013-10-29

申请号：US12886366

申请日：2010-09-20

申请人： Ian Rudolf Bratt ,  Carl G. Ramey ,  Matthew Mattina

发明人： Ian Rudolf Bratt ,  Carl G. Ramey ,  Matthew Mattina

IPC分类号： G06F15/16 ,  G06F13/00

CPC分类号： G06F9/5022 ,  G06F9/4825 ,  G06F9/4881 ,  G06F9/544 ,  G06F11/1482 ,  G06F12/00 ,  G06F12/02 ,  G06F12/0806 ,  G06F12/0808 ,  G06F12/0844 ,  G06F12/0848 ,  G06F12/0864 ,  G06F12/0891 ,  G06F12/10 ,  G06F12/1027 ,  G06F12/12 ,  G06F12/121 ,  G06F12/123 ,  G06F13/4068 ,  G06F13/4221 ,  G06F15/16 ,  G06F15/8023 ,  G06F21/79 ,  G06F2212/502 ,  G06F2212/601 ,  H04L45/08 ,  H04L45/22 ,  H04L45/28 ,  H04L47/823 ,  H04L49/109

摘要： Communicating among cores in a computing system comprising a plurality of cores, each core comprising a processor and a switch, includes: routing a packet from an origin core to a destination core over a route including multiple cores; and at each core in the route before the destination core, routing the packet to the next core in the route according to a respective symbol in a sequence of multiple symbols. The respective symbol has a first symbol value indicating a single likely direction and the respective symbol has a second symbol value indicating multiple less likely directions.

摘要翻译： 在包括多个核心的计算系统中的核心之间进行通信，每个核心包括处理器和交换机，包括：通过包括多个核心的路由将分组从原始核心路由到目的地核心; 并且在目的地核心之前的路由中的每个核心处，根据多个符号序列中的相应符号将分组路由到路由中的下一个核心。 相应的符号具有指示单个可能方向的第一符号值，并且相应的符号具有指示多个较不可能的方向的第二符号值。

公开(公告)号：US20070168712A1

公开(公告)日：2007-07-19

申请号：US11282213

申请日：2005-11-18

申请人： Paul Racunas ,  Matthew Mattina ,  George Chrysos ,  Shubhendu Mukherjee

发明人： Paul Racunas ,  Matthew Mattina ,  George Chrysos ,  Shubhendu Mukherjee

IPC分类号： G06F11/00

CPC分类号： G06F11/1683 ,  G06F11/1637

摘要： Methods of operating two or more devices in lockstep by generating requests at each device, comparing the requests, and forwarding matching requests to a servicing node are described and claimed. A redundant execution system using the methods is also described and claimed.

摘要翻译： 描述并要求保护在每个设备上生成请求，比较请求以及将匹配请求转发到服务节点的锁步骤中的两个或多个设备的操作方法。 还描述并要求保护使用该方法的冗余执行系统。

公开(公告)号：US20060004963A1

公开(公告)日：2006-01-05

申请号：US10882048

申请日：2004-06-30

申请人： Matthew Mattina ,  Antonio Juan-Hormigo ,  Joel Emer ,  Ramon Matas-Navarro

发明人： Matthew Mattina ,  Antonio Juan-Hormigo ,  Joel Emer ,  Ramon Matas-Navarro

IPC分类号： G06F12/00

CPC分类号： G06F12/084 ,  G06F12/0864 ,  G06F12/121 ,  G06F2212/6082

摘要： A method and apparatus for partitioning a shared cache of a chip multi-processor are described. In one embodiment, the method includes a request of a cache block from system memory if a cache miss within a shared cache is detected according to a received request from a processor. Once the cache block is requested, a victim block within the shared cache is selected according to a processor identifier and a request type of the received request. In one embodiment, selection of the victim block according to a processor identifier and request type is based on a partition of a set-associative, shared cache to limit the selection of the victim block from a subset of available cache ways according to the cache partition. Other embodiments are described and claimed.

公开(公告)号：US20050276274A1

公开(公告)日：2005-12-15

申请号：US10855483

申请日：2004-05-28

申请人： Matthew Mattina ,  George Chrysos ,  Stephen Felix

发明人： Matthew Mattina ,  George Chrysos ,  Stephen Felix

IPC分类号： H04L12/427 ,  H04L12/43 ,  H04L12/56 ,  H04L12/28

CPC分类号： H04L12/43 ,  H04L12/427 ,  H04L47/10

摘要： Embodiments of the present invention are related in general to data flow control in a network and in particular to synchronous packet flow control in a ring interconnect. An embodiment of a method may include rejecting an arriving packet at a destination node on a semiconductor chip's ring interconnect, e.g., an unbuffered, synchronous ring interconnect, if all of the destination node's buffers are not available, leaving the rejected packet on the ring interconnect to continue traversing the ring, and accepting the rejected packet upon arrival at the destination node, if a buffer is available. In an alternate embodiment, a method may include tracking the rejected packet as the rejected packet traverses the ring interconnect. An embodiment of an apparatus may include a semiconductor chip having a bidirectional ring interconnect and multiple nodes coupled to the bidirectional ring interconnect. Each node may have a buffer to store packets that arrive on the ring interconnect, if the buffer is available, and to reject packets that arrive, if the buffer is not available. These embodiments provide efficient flow control of packets on unbuffered, synchronous ring interconnects. Exemplary applications include chip multiprocessing.

摘要翻译： 本发明的实施例一般涉及网络中的数据流控制，特别涉及环形互连中的同步分组流控制。 方法的实施例可以包括在半导体芯片的环形互连（例如，无缓冲的同步环形互连）上的目的地节点处拒绝到达的分组，如果所有目的地节点的缓冲器都不可用，则将拒绝的分组留在环形互连 继续遍历环，并且如果缓冲器可用，则在到达目的地节点时接受被拒绝的分组。 在替代实施例中，一种方法可以包括在拒绝的分组穿过环形互连时跟踪被拒绝的分组。 装置的实施例可以包括具有双向环互连和耦合到双向环互连的多个节点的半导体芯片。 每个节点可以具有缓冲器来存储到达环形互连上的分组，如果缓冲器可用，并且如果缓冲器不可用，则拒绝到达的分组。 这些实施例提供了在无缓冲的同步环互连上的分组的有效流控制。 示例性应用包括芯片多处理。

公开(公告)号：US20050091121A1

公开(公告)日：2005-04-28

申请号：US10691176

申请日：2003-10-22

申请人： Mark Charney ,  Ravi Rajwar ,  Pritpal Ahuja ,  Matthew Mattina

发明人： Mark Charney ,  Ravi Rajwar ,  Pritpal Ahuja ,  Matthew Mattina

IPC分类号： G06F12/08 ,  G06F17/60

CPC分类号： G06F12/0813 ,  G06Q30/0601

摘要： A physically distributed cache memory system includes an interconnection network, first level cache memory slices, and second level cache memory slices. The first level cache memory slices are coupled to the interconnection network to generate tagged ordered store requests. Each tagged ordered store requests has a tag including requester identification and a store sequence token. The second level cache memory slices are coupled to the interconnection network to execute ordered store requests in-order across the physically distributed cache memory system in response to each tag of the tagged ordered store requests.

摘要翻译： 物理分布式高速缓冲存储器系统包括互连网络，第一级高速缓存存储器片和第二级高速缓存存储器片。 第一级缓存存储器片耦合到互连网络以生成标记的有序存储请求。 每个标记的有序存储请求都具有包括请求者标识和存储序列令牌的标签。 第二级高速缓存存储器片耦合到互连网络，以响应于标记的有序存储请求的每个标签跨物理分布式高速缓冲存储器系统按顺序执行有序存储请求。

公开(公告)号：US10339059B1

公开(公告)日：2019-07-02

申请号：US14246213

申请日：2014-04-07

申请人： Matthew Mattina

发明人： Matthew Mattina

IPC分类号： G06F12/0817 ,  G06F12/0831

摘要： A flexible, scalable server is described. The server includes plural server nodes each server node including processor cores and switching circuitry configured to couple the processor to a network among the cores with the plurality of cores implementing networking functions within the compute nodes wherein the plurality of cores networking capabilities allow the cores to connect to each other, and to offer a single interface to a network coupled to the server.