摘要:
Embodiments allow a smaller, simpler hardware implementation of an input/output memory management unit (IOMMU) having improved translation behavior that is independent of page table structures and formats. Embodiments also provide device-independent structures and methods of implementation, allowing greater generality of software (fewer specific software versions, in turn reducing development costs).
摘要:
A communication protocol that allows an inserted control packet to immediately follow another control packet can be more robust to single bit errors when the two types of control packets can be distinguished using transmitted control signals to perform packet framing without having to examine the contents of the control packet.
摘要:
In one embodiment, an input/output memory management unit (IOMMU) comprises a cache to cache translation data from memory; and a control unit coupled to the cache. The control unit is configured to implement address translation and memory protection for memory requests sourced by one or more input/output (I/O) devices. The memory requests sourced by the I/O devices travel in one or more first virtual channels, and the control unit is configured to transmit memory requests sourced by the control unit in at least a second virtual channel separate from the first virtual channels.
摘要:
Described is an aggregation device comprising a plurality of virtual network interface cards (vNICs) and an input/output (I/O) processing complex. The vNICs are in communication with a plurality of processing devices. Each processing device has at least one virtual machine (VM). The I/O processing complex is between the vNICs and at least one physical NIC. The I/O processing complex includes at least one proxy NIC and a virtual switch. The virtual switch exchanges data with a processing device of the plurality of processing devices via a communication path established by a vNIC of the plurality of vNICs between the at least one VM and at least one proxy NIC.
摘要翻译:描述了包括多个虚拟网络接口卡(vNIC)和输入/输出(I / O)处理复合体的聚合设备。 vNIC与多个处理设备通信。 每个处理设备具有至少一个虚拟机(VM)。 I / O处理复合体位于vNIC和至少一个物理网卡之间。 I / O处理复合体包括至少一个代理NIC和虚拟交换机。 虚拟交换机通过由至少一个VM和至少一个代理NIC之间的多个vNIC的vNIC建立的通信路径与多个处理设备的处理设备交换数据。
摘要:
A processing system is provided. The processing system includes a first processing unit coupled to a first memory and a second processing unit coupled to a second memory. The second memory comprises a coherent memory and a private memory that is private to the second processing unit.
摘要:
In an embodiment, a method of processing memory requests in a first processing device is provided. The method includes generating a memory request associated with a memory address located in an unpinned memory space managed by an operating system running on a second processing device; and responsive to a determination that the memory address is not resident in a physical memory, transmitting a message to the second processing device. In response to the message, the operating system controls the second processing device to bring the memory address into the physical memory.
摘要:
A method and apparatus for controlling state information retention determines at least a state information save or restore condition for at least one processing circuit such as one or more CPU or GPU cores or pipelines, in an integrated circuit. In response to determining the state information save or restore condition, the method and apparatus controls either or both of saving or restoring of state information for different virtual machines operating on the processing circuit, into corresponding on-die persistent passive variable resistance memory. The state information save or restore condition is a virtual machine level state information save or restore condition. State information for each of differing virtual machines is saved or restored from differing on-die passive variable resistance memory cells that are assigned on a per-virtual machine basis.
摘要:
A method, system, and computer program product are disclosed for providing improved access to accelerated processing device compute resources to user mode applications. The functionality disclosed allows user mode applications to provide commands to an accelerated processing device without the need for kernel mode transitions in order to access a unified ring buffer. Instead, applications are each provided with their own buffers, which the accelerated processing device hardware can access to process commands. With full operating system support, user mode applications are able to utilize the accelerated processing device in much the same way as a CPU.
摘要:
Methods, systems, and computer readable media generalize control registers in the context of memory address translations for I/O devices. A method includes maintaining a table including a plurality of concurrently available control register base pointers each associated with a corresponding input/output (I/O) device, associating each control register base pointer with a first translation from a guest virtual address (GVA) to a guest physical address (GPA) and a second translation from the GPA to a system physical address (SPA), and operating the first and second translations concurrently for the plurality of I/O devices.
摘要:
Described are aggregation devices and methods for interconnecting server nodes. The aggregation device can include an input region, an output region, and a memory switch. The input region includes a plurality of input ports. The memory switch has a shared through silicon via (TSV) memory coupled to the input ports for temporarily storing data received at the input ports from a plurality of source devices. The output region includes a plurality of output ports coupled to the TSV memory. The output ports provide the data to a plurality of destination devices. A memory allocation system coordinates a transfer of the data from the source devices to the TSV memory. The output ports receive and process the data from the TSV memory independently of a communication from the input ports.