公开(公告)号：US20160364350A1

公开(公告)日：2016-12-15

申请号：US15011291

申请日：2016-01-29

Applicant: Apple Inc.

Inventor： Karan Sanghi ,  Vladislav Petkov ,  Radha Kumar Pulyala ,  Saurabh Garg ,  Haining Zhang

IPC: G06F13/28 ,  G06F13/40

CPC classification number: G06F13/28 ,  G06F13/4027 ,  Y02D10/14 ,  Y02D10/151

Abstract: Methods and apparatus for a synchronized multi-directional transfer on an inter-processor communication (IPC) link. In one embodiment, the synchronized multi-directional transfer utilizes one or more buffers which are configured to accumulate data during a first state. The one or more buffers are further configured to transfer the accumulated data during a second state. Data is accumulated during a low power state where one or more processors are inactive, and the data transfer occurs during an operational state where the processors are active. Additionally, in some variants, the data transfer may be performed for currently available transfer resources, and halted until additional transfer resources are made available. In still other variants, one or more of the independently operable processors may execute traffic monitoring processes so as to optimize data throughput of the IPC link.

Abstract translation: 在处理器间通信（IPC）链路上进行同步多方向传输的方法和装置。 在一个实施例中，同步多向​​传输利用被配置为在第一状态期间累积数据的一个或多个缓冲器。 一个或多个缓冲器还被配置为在第二状态期间传送累积的数据。 在一个或多个处理器不活动的低功率状态期间，数据被累积，并且数据传输在处理器处于活动状态的操作状态期间发生。 此外，在一些变型中，可以对当前可用的传输资源执行数据传输，并且停止直到额外的传输资源可用。 在其他变型中，一个或多个可独立操作的处理器可以执行流量监控过程，以便优化IPC链路的数据吞吐量。

公开(公告)号：US20160103689A1

公开(公告)日：2016-04-14

申请号：US14879024

申请日：2015-10-08

Applicant: Apple Inc.

Inventor： Karan Sanghi ,  Saurabh Garg ,  Haining Zhang

IPC: G06F9/44 ,  G06F13/42

CPC classification number: G06F1/3293 ,  G06F1/3228 ,  G06F1/3243 ,  G06F1/3287 ,  G06F9/4403 ,  G06F9/4405 ,  G06F9/4411 ,  G06F11/1417 ,  G06F11/1471 ,  G06F11/1474 ,  G06F13/4282 ,  G06F2201/805 ,  G06F2201/87 ,  Y02D10/122 ,  Y02D10/14 ,  Y02D10/151 ,  Y02D10/152 ,  Y02D10/171

Abstract: Methods and apparatus for an inter-processor communication (IPC) link between two (or more) independently operable processors. In one aspect, the IPC protocol is based on a “shared” memory interface for run-time processing (i.e., the independently operable processors each share (either virtually or physically) a common memory interface). In another aspect, the IPC communication link is configured to support a host driven boot protocol used during a boot sequence to establish a basic communication path between the peripheral and the host processors. Various other embodiments described herein include sleep procedures (as defined separately for the host and peripheral processors), and error handling.

Abstract translation: 两个（或多个）可独立操作的处理器之间的处理器间通信（IPC）链接的方法和装置。 在一个方面，IPC协议基于用于运行时处理的“共享”存储器接口（即，独立可操作的处理器每个共享（虚拟或物理上）公共存储器接口）。 在另一方面，IPC通信链路被配置为支持在引导序列期间使用的主机驱动的引导协议，以在外围设备和主处理器之间建立基本通信路径。 本文描述的各种其他实施例包括睡眠过程（如针对主机和外围处理器分别定义的）和错误处理。

公开(公告)号：US20130332156A1

公开(公告)日：2013-12-12

申请号：US13775100

申请日：2013-02-22

Applicant: APPLE INC.

Inventor： Onur Ergin Tackin ,  Sinan Karahan ,  Lalin S. Theverapperuma ,  Tiange Shao ,  Haining Zhang ,  Arun G. Mathias

IPC: H04R29/00 ,  G10L21/0216

CPC classification number: H04R29/004 ,  G10L21/0216 ,  G10L25/78 ,  H03G3/3005 ,  H03G3/3089 ,  H04M1/6008 ,  H04M1/6041 ,  H04M2250/12 ,  H04R3/005 ,  H04R3/02 ,  H04R2499/11

Abstract: The disclosed system and method for a mobile device combines information derived from onboard sensors with conventional signal processing information derived from a speech or audio signal to assist in noise and echo cancellation. In some implementations, an Angle and Distance Processing (ADP) module is employed on a mobile device and configured to provide runtime angle and distance information to an adaptive beamformer for canceling noise signals, provides a means for building a table of filter coefficients for adaptive filters used in echo cancellation, provides faster and more accurate Automatic Gain Control (AGC), provides delay information for a classifier in a Voice Activity Detector (VAD), provides a means for automatic switching between a speakerphone and handset mode of the mobile device, or primary microphone and reference microphones and assists in separating echo path changes from double talk.

Abstract translation: 所公开的用于移动设备的系统和方法将从车载传感器获得的信息与从语音或音频信号导出的常规信号处理信息相结合，以帮助噪声和回波消除。 在一些实现中，在移动设备上采用角度和距离处理（ADP）模块，并且被配置为向自适应波束形成器提供运行时间角度和距离信息以消除噪声信号，提供用于建立自适应滤波器的滤波器系数表的装置 用于回声消除，提供更快更准确的自动增益控制（AGC），为语音活动检测器（VAD）中的分类器提供延迟信息，提供了在移动设备的免提电话和手机模式之间自动切换的手段，或 主麦克风和参考麦克风，有助于将回声路径变化与双方通话分离。

公开(公告)号：US10789198B2

公开(公告)日：2020-09-29

申请号：US16450767

申请日：2019-06-24

Applicant: Apple Inc.

Inventor： Vladislav Petkov ,  Saurabh Garg ,  Karan Sanghi ,  Haining Zhang

IPC: G06F15/17 ,  G06F13/42 ,  H04W4/80

Abstract: Methods and apparatus for data transmissions over an inter-processor communication (IPC) link between two (or more) independently operable processors. In one embodiment, the IPC link is configured to enable an independently operable processor to transact data to another independently operable processor, while obviating transactions (such as via direct memory access) by encapsulating a payload within a data structure. For example, a host processor may insert the payload into a transfer descriptor (TD), and transmit the TD to a peripheral processor. The host processor may also include a head index and/or a tail index within a doorbell message sent to the peripheral processor, obviating another access of memory. The peripheral processor may perform similar types of transactions via a completion descriptor (CD) sent to the host processor. In some variants, the peripheral may be a Bluetooth-enabled device optimized for low-latency, low-power, and/or low-throughput transactions.

公开(公告)号：US10684670B2

公开(公告)日：2020-06-16

申请号：US16390998

申请日：2019-04-22

Applicant: Apple Inc.

Inventor： Karan Sanghi ,  Saurabh Garg ,  Haining Zhang

IPC: G06F9/00 ,  G06F1/3293 ,  G06F1/3287 ,  G06F13/42 ,  G06F9/4401 ,  G06F1/3228 ,  G06F1/3234 ,  G06F11/14

Abstract: Methods and apparatus for an inter-processor communication (IPC) link between two (or more) independently operable processors. In one aspect, the IPC protocol is based on a “shared” memory interface for run-time processing (i.e., the independently operable processors each share (either virtually or physically) a common memory interface). In another aspect, the IPC communication link is configured to support a host driven boot protocol used during a boot sequence to establish a basic communication path between the peripheral and the host processors. Various other embodiments described herein include sleep procedures (as defined separately for the host and peripheral processors), and error handling.

公开(公告)号：US10552352B2

公开(公告)日：2020-02-04

申请号：US16056374

申请日：2018-08-06

Applicant: Apple Inc.

Inventor： Karan Sanghi ,  Vladislav Petkov ,  Radha Kumar Pulyala ,  Saurabh Garg ,  Haining Zhang

IPC: G06F13/28 ,  G06F13/40

Abstract: Methods and apparatus for a synchronized multi-directional transfer on an inter-processor communication (IPC) link. In one embodiment, the synchronized multi-directional transfer utilizes one or more buffers which are configured to accumulate data during a first state. The one or more buffers are further configured to transfer the accumulated data during a second state. Data is accumulated during a low power state where one or more processors are inactive, and the data transfer occurs during an operational state where the processors are active. Additionally, in some variants, the data transfer may be performed for currently available transfer resources, and halted until additional transfer resources are made available. In still other variants, one or more of the independently operable processors may execute traffic monitoring processes so as to optimize data throughput of the IPC link.

公开(公告)号：US10551906B2

公开(公告)日：2020-02-04

申请号：US16133543

申请日：2018-09-17

Applicant: Apple Inc.

Inventor： Karan Sanghi ,  Saurabh Garg ,  Haining Zhang

IPC: G06F13/12 ,  G06F12/00 ,  G06F1/3293 ,  G06F1/3287 ,  G06F13/42 ,  G06F9/4401 ,  G06F1/3228 ,  G06F1/3234 ,  G06F11/14

Abstract: Methods and apparatus for an inter-processor communication (IPC) link between two (or more) independently operable processors. In one aspect, the IPC protocol is based on a “shared” memory interface for run-time processing (i.e., the independently operable processors each share (either virtually or physically) a common memory interface). In another aspect, the IPC communication link is configured to support a host driven boot protocol used during a boot sequence to establish a basic communication path between the peripheral and the host processors. Various other embodiments described herein include sleep procedures (as defined separately for the host and peripheral processors), and error handling.

公开(公告)号：US10372199B2

公开(公告)日：2019-08-06

申请号：US15721200

申请日：2017-09-29

Applicant: Apple Inc.

Inventor： Karan Sanghi ,  Saurabh Garg ,  Haining Zhang

IPC: G06F11/00 ,  G06F1/3293 ,  G06F1/3287 ,  G06F13/42 ,  G06F9/4401 ,  G06F11/14 ,  G06F1/3228 ,  G06F1/3234

Abstract: Methods and apparatus for an inter-processor communication (IPC) link between two (or more) independently operable processors. In one aspect, the IPC protocol is based on a “shared” memory interface for run-time processing (i.e., the independently operable processors each share (either virtually or physically) a common memory interface). In another aspect, the IPC communication link is configured to support a host driven boot protocol used during a boot sequence to establish a basic communication path between the peripheral and the host processors. Various other embodiments described herein include sleep procedures (as defined separately for the host and peripheral processors), and error handling.

公开(公告)号：US20190155757A1

公开(公告)日：2019-05-23

申请号：US16259543

申请日：2019-01-28

Applicant: Apple Inc.

Inventor： Saurabh Garg ,  Karan Sanghi ,  Vladislav Petkov ,  Haining Zhang

IPC: G06F12/14 ,  G06F12/1081

Abstract: Methods and apparatus for registering and handling access violations of host memory. In one embodiment, a peripheral processor receives one or more window registers defining an extent of address space accessible from a host processor; responsive to an attempt to access an extent of address space outside of the extent of accessible address space, generates an error message; stores the error message within a violation register; and resumes operation of the peripheral processor upon clearance of the stored error message.

公开(公告)号：US10191859B2

公开(公告)日：2019-01-29

申请号：US15271109

申请日：2016-09-20

Applicant: Apple Inc.

Inventor： Saurabh Garg ,  Karan Sanghi ,  Vladislav Petkov ,  Haining Zhang

IPC: G06F12/00 ,  G06F12/14 ,  G06F12/1081

Abstract: Methods and apparatus for providing access to a shared memory resource. In one embodiment, a first processor generates a first window register associated with the shared memory resource; and transmits the first window register from the first processor to a second processor, the first window register defining a first extent of address space within the shared memory resource that is directly accessible by the second processor without requiring a performance of arbitration operations by the first processor.