中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

44 records (took 0.026 seconds)

    Video Pipeline
    31.
    发明申请
    Video Pipeline 有权

    公开(公告)号：US20240394952A1

    公开(公告)日：2024-11-28

    申请号：US18797340

    申请日：2024-08-07

    Applicant: Apple Inc.

    Inventor： Arthur Y Zhang ,  Ray L. Chang ,  Timothy R. Oriol ,  Ling Su ,  Gurjeet S. Saund ,  Guy Cote ,  Jim C. Chou ,  Hao Pan ,  Tobias Eble ,  Avi Bar-Zeev ,  Sheng Zhang ,  Justin A. Hensley ,  Geoffrey Stahl

    IPC: G06T15/00 ,  G06F3/01 ,  G06T3/18 ,  G06T9/00 ,  H04W76/10 ,  H04W88/08

    Abstract: A mixed reality system that includes a device and a base station that communicate via a wireless connection The device may include sensors that collect information about the user's environment and about the user. The information collected by the sensors may be transmitted to the base station via the wireless connection. The base station renders frames or slices based at least in part on the sensor information received from the device, encodes the frames or slices, and transmits the compressed frames or slices to the device for decoding and display. The base station may provide more computing power than conventional stand-alone systems, and the wireless connection does not tether the device to the base station as in conventional tethered systems. The system may implement methods and apparatus to maintain a target frame rate through the wireless link and to minimize latency in frame rendering, transmittal, and display.

    Lossy compression techniques
    32.
    发明授权
    Lossy compression techniques 有权

    公开(公告)号：US12052038B2

    公开(公告)日：2024-07-30

    申请号：US18302513

    申请日：2023-04-18

    Applicant: Apple Inc.

    Inventor： Tyson J. Bergland ,  Karthik Ramani ,  Stephan Lachowsky ,  Justin A. Hensley ,  Davoud A. Jamshidi

    IPC: H03M7/30 ,  H04N19/176 ,  H04N19/182

    CPC classification number: H03M7/3059 ,  H04N19/176 ,  H04N19/182

    Abstract: Techniques are disclosed relating to compression of pixel data using different quantization for different regions of a block of pixels being compressed. In some embodiments, compression circuitry is configured to determine, for multiple components included in pixels of the block of pixels being compressed, respective smallest and greatest component values in respective regions of the block of pixels. The compression circuitry may determine, based on the determined smallest and greatest component values, to use a first number of bits to represent delta values relative to a base value for a first component in a first region and a second, different number of bits to represent delta values relative to a base value for a second component in the first region. The compression circuitry may then quantize delta values for the first and second components of pixels in the first region of the block of pixels using the determined first and second numbers of bits. In some embodiments, the compression circuitry determines whether to provide cross-component bit sharing within a region.

    On-demand memory allocation
    34.
    发明授权
    On-demand memory allocation 有权

    公开(公告)号：US11829298B2

    公开(公告)日：2023-11-28

    申请号：US16804128

    申请日：2020-02-28

    Applicant: Apple Inc.

    Inventor： Justin A. Hensley ,  Karl D. Mann ,  Yoong Chert Foo ,  Terence M. Potter ,  Frank W. Liljeros ,  Ralph C. Taylor

    IPC: G06F12/1018 ,  G06F12/084 ,  G06F30/392

    CPC classification number: G06F12/1018 ,  G06F12/084 ,  G06F30/392 ,  G06F2212/622 ,  G06F2212/651

    Abstract: Techniques are disclosed relating to dynamically allocating and mapping private memory for requesting circuitry. Disclosed circuitry may receive a private address and translate the private address to a virtual address (which an MMU may then translate to physical address to actually access a storage element). In some embodiments, private memory allocation circuitry is configured to generate page table information and map private memory pages for requests if the page table information is not already setup. In various embodiments, this may advantageously allow dynamic private memory allocation, e.g., to efficiently allocate memory for graphics shaders with different types of workloads. Disclosed caching techniques for page table information may improve performance relative to traditional techniques. Further, disclosed embodiments may facilitate memory consolidation across a device such as a graphics processor.

    Graphics Memory Space for Shader Core
    36.
    发明申请
    Graphics Memory Space for Shader Core 有权

    公开(公告)号：US20220148249A1

    公开(公告)日：2022-05-12

    申请号：US17103462

    申请日：2020-11-24

    Applicant: Apple Inc.

    Inventor： Terence M. Potter ,  Yoong Chert Foo ,  Ali Rabbani Rankouhi ,  Justin A. Hensley ,  Jonathan M. Redshaw

    IPC: G06T15/00 ,  G06F9/50 ,  G06F9/38 ,  G06T1/60

    Abstract: Disclosed techniques relate to memory space management for graphics processing. In some embodiments, first and second graphics cores are configured to execute instructions for multiple threadgroups. In some embodiments, the threads groups include a first threadgroup with multiple single-instruction multiple-data (SIMD) groups configured to execute a first shader program and a second threadgroup with multiple SIMD groups configured to execute a second, different shader program. Control circuitry may be configured to provide access to data stored in memory circuitry according to a shader memory space. The shader memory space may be accessible to threadgroups executed by the first graphics shader core, including the first and second threadgroups, but is not accessible to threadgroups executed by the second graphics shader core. Disclosed techniques may reduce latency, increase bandwidth available to the shader, reduce coherency cost, or any combination thereof.

    Ray Intersection Data Structure with Many-to-Many Mapping between Bounding Regions and Primitives
    37.
    发明申请
    Ray Intersection Data Structure with Many-to-Many Mapping between Bounding Regions and Primitives 有权

    公开(公告)号：US20220036652A1

    公开(公告)日：2022-02-03

    申请号：US17103352

    申请日：2020-11-24

    Applicant: Apple Inc.

    Inventor： Ali Rabbani Rankouhi ,  Christopher A. Burns ,  Justin A. Hensley

    IPC: G06T17/10 ,  G06T15/06 ,  G06T15/00 ,  G06T1/20

    Abstract: Disclosed techniques relate to an acceleration data structure for ray intersection with a many-to-many mapping between bounding regions and primitives. In some embodiments, one or more graphics processors access data for multiple graphics primitives in a graphics scene and generate a spatially organized data structure. Some nodes of the data structure indicate graphics primitives and some nodes indicate coordinates of bounding regions in the graphics scene. In some embodiments, the spatially organized data structure includes a node with a bounding region for which multiple primitives are indicated as children and also includes a primitive for which multiple bounding regions are indicated as parents. Disclosed techniques may generate bounding regions that closely fit primitives, which may reduce primitive testing for ray tracing. This in turn may increase performance or reduce power consumption relative to traditional techniques.

    SIMD Group Formation Techniques for Primitive Testing associated with Ray Intersect Traversal
    38.
    发明申请
    SIMD Group Formation Techniques for Primitive Testing associated with Ray Intersect Traversal 有权

    公开(公告)号：US20220036638A1

    公开(公告)日：2022-02-03

    申请号：US17103406

    申请日：2020-11-24

    Applicant: Apple Inc.

    Inventor： Ali Rabbani Rankouhi ,  Christopher A. Burns ,  Justin A. Hensley ,  Luca Iuliano ,  Jonathan M. Redshaw

    IPC: G06T15/06 ,  G06T15/00

    Abstract: Disclosed techniques relate to primitive testing associated with ray intersection processing for ray tracing. In some embodiments, shader circuitry executes a first SIMD group that includes a ray intersect instruction for a set of rays. Ray intersect circuitry traverses, in response to the ray intersect instruction, multiple nodes in a spatially organized acceleration data structure (ADS). In response to reaching a node of the ADS that indicates one or more primitives, the apparatus forms a second SIMD group that executes one or more instructions to determine whether a set of rays that have reached the node intersect the one or more primitives. The shader circuitry may execute the first SIMD group to shade one or more primitives that are indicated as intersected based on results of execution of the second SIMD group. Thus, disclosed techniques may use both dedicated ray intersect circuitry and dynamically formed SIMD groups executed by shader processors to detect ray intersection.

    Multi-space rendering with configurable transformation parameters
    39.
    发明授权
    Multi-space rendering with configurable transformation parameters 有权

    公开(公告)号：US11113788B2

    公开(公告)日：2021-09-07

    申请号：US17001007

    申请日：2020-08-24

    Applicant: Apple Inc.

    Inventor： Justin A. Hensley ,  Karl D. Mann ,  Ralph C. Taylor ,  Randall R. Rauwendaal ,  Jonathan M. Redshaw

    IPC: G06T3/40 ,  G06T15/40 ,  G06F30/30 ,  G06F3/01 ,  G06T15/00 ,  G06T15/60 ,  G06F119/18

    Abstract: Techniques are disclosed relating to rendering graphics objects. In some embodiments, a graphics unit is configured to transform graphics objects from a virtual space into a second space according to different transformation parameters for different portions of the second space. This may result in sampling different portions of the virtual space at different sample rates, which may reduce the number of samples required in various stages of the rendering process. In the disclosed techniques, transformation may occur prior to rasterization and shading, which may further reduce computation and power consumption in a graphics unit, improve image quality as displayed to a user, and/or reduce bandwidth usage or latency of video content on a network. In some embodiments, a transformed image may be viewed through a distortion-compensating lens or resampled prior to display.

    Video pipeline
    40.
    发明授权
    Video pipeline 有权

    公开(公告)号：US11043018B2

    公开(公告)日：2021-06-22

    申请号：US16662952

    申请日：2019-10-24

    Applicant: Apple Inc.

    Inventor： Arthur Y Zhang ,  Ray L. Chang ,  Timothy R. Oriol ,  Ling Su ,  Gurjeet S. Saund ,  Guy Cote ,  Jim C. Chou ,  Hao Pan ,  Tobias Eble ,  Avi Bar-Zeev ,  Sheng Zhang ,  Justin A. Hensley ,  Geoffrey Stahl

    IPC: G06F3/01 ,  G06T15/00 ,  H04W76/10 ,  G06T3/00 ,  G06T9/00 ,  H04W88/08

    Abstract: A mixed reality system that includes a device and a base station that communicate via a wireless connection The device may include sensors that collect information about the user's environment and about the user. The information collected by the sensors may be transmitted to the base station via the wireless connection. The base station renders frames or slices based at least in part on the sensor information received from the device, encodes the frames or slices, and transmits the compressed frames or slices to the device for decoding and display. The base station may provide more computing power than conventional stand-alone systems, and the wireless connection does not tether the device to the base station as in conventional tethered systems. The system may implement methods and apparatus to maintain a target frame rate through the wireless link and to minimize latency in frame rendering, transmittal, and display.

Patent Agency Ranking