公开(公告)号：US20220300022A1

公开(公告)日：2022-09-22

申请号：US17658408

申请日：2022-04-07

Applicant: Apple Inc.

Inventor： Shawn Searles ,  Victor Zyuban ,  Mohamed Abu-Rahma

IPC: G05F1/575 ,  H03K17/22

Abstract: A voltage regulator circuit may generate a regulated voltage level using a voltage level of a feedback node. The regulated voltage level may be distributed, via a power distribution network, to package power supply node of a package, into which an integrated circuit has been mounted. Power switches included in the integrated circuit may couple the package power supply node to respective local power supply nodes in the integrated circuit. A particular power switch may selectively couple different ones of the local power supply nodes to the feedback node, allowing the voltage regulator circuit to compensate for reductions in the regulated voltage level due to the power distribution network, as well as adjust the regulated voltage level based on power consumptions of load circuits coupled to the local power supply nodes.

公开(公告)号：US20220029536A1

公开(公告)日：2022-01-27

申请号：US16936410

申请日：2020-07-22

Applicant: Apple Inc.

Inventor： Victor Zyuban ,  Norman J. Rohrer ,  Shawn Searles

IPC: H02M3/158 ,  H03K5/24

Abstract: A converter circuit, included in a power converter circuit, may generate a given voltage level on a regulated power supply node of a computer system. A control circuit may monitor a voltage level and assert a control signal in response to a determination that a regulation event has occurred. A boost converter circuit, included in the power converter circuit, may inject charge into to the regulated power supply node via a capacitor, in response to an assertion of the control signal.

公开(公告)号：US11152046B1

公开(公告)日：2021-10-19

申请号：US16931870

申请日：2020-07-17

Applicant: Apple Inc.

Inventor： Jaroslav Raszka ,  Shahzad Nazar ,  Jaemyung Lim ,  Mohamed H. Abu-Rahma ,  Victor Zyuban

IPC: G11C11/413 ,  G11C8/12 ,  G11C5/14

Abstract: A memory array that provides an internal retention voltage without a voltage regulator is disclosed. The memory array includes a first group of bit cells coupled between the power supply rail and a ground switch and a second group of bit cells coupled to a retention select circuit. The retention select circuit is coupled to the ground for the first group of bit cells and the power supply rail. The ground switch and the retention select circuit may be operated to switch the bit cells between a nominal operating voltage and a retention voltage. The retention voltage is provided during inactive periods of the memory array to maintain data in the bit cells during the inactive periods.

公开(公告)号：US10187045B2

公开(公告)日：2019-01-22

申请号：US15217122

申请日：2016-07-22

Applicant: Apple Inc.

Inventor： Victor Zyuban ,  Norman Rohrer ,  Nimish Kabe ,  Neela Lohith Penmetsa

IPC: H03K5/05 ,  H03K19/21 ,  H03K3/037

Abstract: Techniques are disclosed relating to dual-edge triggered (DET) clock gater circuitry. In some embodiments, an apparatus includes a first series of DET clock gater circuits configured, when the DET clock gater circuits are not gating an input clock signal, to provide an output clock signal to sequential circuitry. In some embodiments, ones of the DET clock gater circuits are controlled by respective control signals and are configured to maintain a mode indicator indicating whether or not the DET clock gater circuit is inverting the polarity of its input clock when generating an output clock. In some embodiments, the apparatus also includes a first adjustable delay circuit configured to adjust delay imposed on the output clock signal from the first series of DET clock gater circuits based on the number of DET clock gater circuits in the series that are in a particular mode.

公开(公告)号：US09660620B1

公开(公告)日：2017-05-23

申请号：US15217669

申请日：2016-07-22

Applicant: Apple Inc.

Inventor： Victor Zyuban ,  Nimish Kabe

IPC: H03K5/01 ,  G05B19/41 ,  H03K19/21 ,  H03K5/00

CPC classification number: H03K5/01 ,  H03K5/134 ,  H03K19/0016 ,  H03K19/21 ,  H03K2005/00019 ,  H03K2005/00065 ,  H03K2005/00234

Abstract: Techniques are disclosed relating to dual-edge triggered clock gater circuitry. In some embodiments, an apparatus includes dual-edge triggered clock gater circuitry configured to generate an output signal based on an input clock signal and a control signal that indicates whether to gate the input clock signal. In some embodiments, the clock gater circuitry includes first and second storage elements. In some embodiments, the clock gater circuitry includes multiplexer circuitry that selects between outputs of the first and second storage elements to generate the output signal. In some embodiments, the clock gater circuitry includes a third storage element configured to store an indication of which of the first and second storage elements stores a first digital value and which stores an inverse of the first digital value when not gating. In some embodiments, the clock gater circuitry includes a buffering element configured, when gating, to copy data stored in one of the first and second storage elements to the other of the first and second storage elements.