公开(公告)号：US10956205B2

公开(公告)日：2021-03-23

申请号：US15396985

申请日：2017-01-03

Applicant: ARM Limited

Inventor： Alistair Crone Bruce ,  Andrew David Tune

IPC: G06F9/46 ,  G06F9/54 ,  G06F13/16 ,  G06F3/00 ,  G06F11/07

Abstract: Data processing apparatus comprises one or more transaction issuing devices configured to issue data processing transactions to be handled by a downstream device and to receive a completion acknowledgement in respect of each completed transaction; each transaction issuing device having associated transaction regulator circuitry configured to allow that transaction issuing device to issue transactions subject to a limit on a maximum number of outstanding transactions, an outstanding transaction being a transaction which has been issued but for which a completion acknowledgement has not yet been received; in which the downstream device is configured to issue an indication to a transaction issuing device, to authorize a change by the transaction regulator circuitry of the limit applicable to outstanding transactions by that transaction issuing device.

公开(公告)号：US10761561B2

公开(公告)日：2020-09-01

申请号：US15989228

申请日：2018-05-25

Applicant: Arm Limited

Inventor： Saira Samar Malik ,  David Joseph Hawkins ,  Andrew David Tune ,  Guanghui Geng ,  Julian Jose Hilgemberg Pontes

IPC: G06F1/12 ,  G06F30/39

Abstract: An apparatus and method for transmitting signals between two clock domains in which at least one of a phase and a frequency of clock signals in the two clock domains is misaligned. The apparatus includes a first primary interface and a first redundant interface in the first clock domain for receiving a primary signal and a first checking signal respectively, and a second primary interface and second redundant interface in the second clock domain for outputting the primary signal and a second redundant signal respectively. The primary signal and the checking signals are separated by a predetermined time delay and the second checking signal is generated in the second clock domain based on the primary signal. Checking circuitry is provided in the second clock domain to perform an error checking procedure based on the two checking signals and to provide the second checking signal to the second redundant interface.

公开(公告)号：US10579469B2

公开(公告)日：2020-03-03

申请号：US15989224

申请日：2018-05-25

Applicant: Arm Limited

Inventor： Guanghui Geng ,  Andrew David Tune

IPC: G06F7/02 ,  H03M13/00 ,  G06F11/10 ,  G06F13/40

Abstract: An interconnection network for providing data transfer between a plurality of nodes of an integrated circuit comprises a number of endpoints for exchanging data with respective nodes of the integrated circuit, a primary network to route a primary payload from a source endpoint to a destination endpoint; and a redundant network to route, to the destination endpoint, a redundant payload comprising a first check code calculated based on at least a portion of the primary payload, the first check code having fewer bits than said at least a portion of the primary payload. The destination endpoint comprises error checking circuitry to perform an error checking operation to calculate a second check code based on the primary payload received via the primary network, and verify integrity of the primary payload based on a comparison of the second check code with the first check code received via the redundant network.

公开(公告)号：US10303624B2

公开(公告)日：2019-05-28

申请号：US15273932

申请日：2016-09-23

Applicant: ARM LIMITED

Inventor： Andrew David Tune ,  Peter Andrew Riocreux ,  Alessandro Grande

IPC: H04L12/937 ,  G06F13/14

Abstract: Arbitrating and multiplexing circuitry for performing an arbitration between a plurality of inputs and a selection of at least one of said plurality of inputs to provide an output comprises arbitrating tree circuitry having X arbitrating levels, where X is an integer greater than one; and multiplexing tree circuitry having Y multiplexing levels, where Y is an integer greater than one; wherein (i) said Y multiplexing levels comprise a first set of said multiplexing levels upstream of a second set of said multiplexing levels; (ii) said first set of said multiplexing levels is configured to operate in parallel with at least some of said X arbitrating levels, whereby said first set of multiplexing levels is configured to perform a partial selection in parallel with said arbitration performed by said X arbitrating levels; and (iii) said second set of said multiplexing levels is configured to operate in series with said X arbitrating levels, whereby said second set of multiplexing levels completes said selection to provide said output following completion of and in dependence upon said arbitration.

公开(公告)号：US09977742B2

公开(公告)日：2018-05-22

申请号：US15133311

申请日：2016-04-20

Applicant: ARM LIMITED

Inventor： Andrew David Tune ,  Sean James Salisbury

IPC: G06F12/08 ,  G06F12/0817 ,  G06F12/0831 ,  G06F12/12

CPC classification number: G06F12/0817 ,  G06F12/0833 ,  G06F12/12 ,  G06F2212/1016

Abstract: A cache coherency controller comprises a directory indicating, for memory addresses cached by a group of two or more cache memories in a coherent cache structure, which of the cache memories are caching those memory addresses, the directory being associative so that multiple memory addresses map to an associative set of more than one directory entry; and control logic responsive to a memory address to be newly cached, and configured to detect whether one or more of the set of directory entries mapped to that memory address is available for storage of an indication of which of the two or more cache memories are caching that memory address; the control logic being configured so that when all of the set of directory entries mapped to that memory address are occupied, the control logic is configured to select one of the set of directory entries as a directory entry to be overwritten and the corresponding cached information to be invalidated, the control logic being configured to select a directory entry to be overwritten, from the set of directory entries, in dependence upon which of the group of two or more cache memories is indicated by that directory entry, according to a likelihood of selection amongst the two or more cache memories.

公开(公告)号：US09852088B2

公开(公告)日：2017-12-26

申请号：US14628331

申请日：2015-02-23

Applicant: ARM LIMITED

Inventor： Andrew David Tune ,  Daniel Sara ,  Sean James Salisbury ,  Arthur Laughton ,  Peter Andrew Riocreux

IPC: G06F13/16 ,  G06F13/00

CPC classification number: G06F13/1626 ,  G06F13/1673

Abstract: A system-on-check integrated circuit 2 includes interconnect circuitry 4 connecting a plurality of transaction sources to a plurality of transaction destinations. The interconnect circuitry 4 includes a reorder buffer for buffering access transactions and hazard checking circuitry 46, 48, 50, 52 for performing hazard checks, such as point-of-serialization checks and identifier reuse checks. Check suppression circuitry 62, 64, 66, 68 serves to suppress one or more hazard checks depending upon one or more state variables that themselves depend upon access transactions other than the access transaction for which the hazard checking is or is not to be suppressed. As an example, hazard checking may be suppressed if it is known that there are no other access transactions currently buffered within the reorder buffer 26 or alternatively no other access transactions from the same transaction source buffered within the reorder buffer 26.

公开(公告)号：US09639470B2

公开(公告)日：2017-05-02

申请号：US14468536

申请日：2014-08-26

Applicant: ARM LIMITED

Inventor： Sean James Salisbury ,  Andrew David Tune ,  Jamshed Jalal ,  Mark David Werkheiser

IPC: G06F12/08 ,  G06F12/0831

CPC classification number: G06F12/0833 ,  G06F12/0831 ,  G06F2212/1016

Abstract: An interconnect has coherency control circuitry for performing coherency control operations and a snoop filter for identifying which devices coupled to the interconnect have cached data from a given address. When an address is looked up in the snoop filter and misses, and there is no spare snoop filter entry available, then the snoop filter selects a victim entry corresponding to a victim address, and issues an invalidate transaction for invalidating locally cached copies of the data identified by the victim. The coherency control circuitry for performing coherency checking operations for data access transactions is reused for performing coherency control operations for the invalidate transaction issued by the snoop filter. This greatly reduces the circuitry complexity of the snoop filter.

公开(公告)号：US09311244B2

公开(公告)日：2016-04-12

申请号：US14467469

申请日：2014-08-25

Applicant: ARM LIMITED

Inventor： Sean James Salisbury ,  Andrew David Tune ,  Daniel Sara

IPC: G06F12/02 ,  G06F12/08

CPC classification number: G06F12/0831 ,  G06F2212/1016 ,  G06F2212/621

Abstract: An interconnect has transaction tracking circuitry for enforcing ordering of a set of data access transactions so that they are issued to slave devices in an order in which they are received from master devices. The transaction tracking circuitry is reused for also enforcing ordering of snoop transactions which are triggered by the set of data access transactions, for snooping master devices identified by a snoop filter as holding cache data for the target address of the transactions.

Abstract translation: 互连具有用于实施一组数据访问事务的排序的事务跟踪电路，使得它们以从主设备接收的顺序被发布到从设备。 交易跟踪电路被重新用于执行由一组数据访问事务触发的窥探事务的排序，用于窥探由窥探过滤器识别的主设备作为事务的目标地址的缓存数据。

公开(公告)号：US09304923B2

公开(公告)日：2016-04-05

申请号：US13795680

申请日：2013-03-12

Applicant: ARM LIMITED

Inventor： Andrew David Tune

IPC: G06F12/00 ,  G06F12/08

CPC classification number: G06F12/0817 ,  G06F12/0808 ,  G06F12/0831 ,  G06F12/0833 ,  G06F12/0864 ,  G06F12/0895

Abstract: A data processing systems employing a coherent memory system comprises multiple main cache memories. An inclusive snoop directory memory stores directory lines. Each directory line includes a directory tag and multiple snoop vectors. Each snoop vector relates to a span of memory addresses corresponding to the cache line size within the main cache memories.

Abstract translation: 采用相干存储器系统的数据处理系统包括多个主高速缓存存储器。 包含snoop目录的内存存储目录行。 每个目录行包括目录标签和多个侦听向量。 每个窥探向量涉及与主高速缓冲存储器内的高速缓存行大小相对应的存储器地址的跨度。

公开(公告)号：US09213660B2

公开(公告)日：2015-12-15

申请号：US13918025

申请日：2013-06-14

Applicant: ARM Limited

Inventor： Sean James Salisbury ,  Andrew David Tune ,  Alistair Crone Bruce

IPC: G06F13/00 ,  G06F13/362

CPC classification number: G06F13/362 ,  G06F13/37

Abstract: A data processing apparatus is provided with a master device and a slave device which communicate via communication circuitry. The slave device is associated with a predetermined number of permission tokens that is equal to a maximum number of currently pending messages that can be accepted for processing from the communication circuitry by that slave device. The slave device transmits these permission tokens to the master device. The master device takes exclusive temporary possession of the permission tokens that it receives such that the permission tokens are then no longer available to any other master device. A master device initiates a message to a slave device when the master device has exclusive temporary possession of a permission token for that slave device. When the master device has initiated its message, then it relinquishes the exclusive temporary possession of the permission token such that it is then available for other devices.

Abstract translation: 数据处理装置具有通过通信电路进行通信的主设备和从设备。 从设备与预定数量的权限令牌相关联，该权限令牌等于可由该从设备从通信电路接受用于处理的当前待定消息的最大数量。 从设备将这些权限令牌发送到主设备。 主设备占用其接收到的权限令牌的专属临时占用，使得许可令牌不再可用于任何其他主设备。 当主设备对该从设备具有独占临时拥有权限令牌时，主设备向从设备发起消息。 当主设备已经发起其消息时，它放弃对该权限令牌的独占临时拥有，使得其可用于其他设备。