公开(公告)号：US20200014373A1

公开(公告)日：2020-01-09

申请号：US16026946

申请日：2018-07-03

Applicant: Arm Limited

Inventor： Shri Sagar Dwivedi ,  Fakhruddin Ali Bohra ,  Lalit Gupta ,  Yew Keong Chong ,  Gus Yeung

IPC: H03K5/06 ,  G06F12/0804

Abstract: Various implementations described herein are directed to an integrated circuit having clock generation circuitry that receives an input clock signal and provides a first clock signal having a first pulse width. The integrated circuit includes first pulse-stretching circuitry coupled between the clock generation circuitry and input latch control circuitry. The first pulse-stretching circuitry receives the first clock signal and provides a second clock signal to the input latch control circuitry based on an enable signal. The second clock signal has a second pulse width that is at least greater than the first pulse width. The integrated circuit may include second pulse-stretching circuitry coupled between the clock generation circuitry and read-write circuitry. The second pulse-stretching circuitry provides a third clock signal to the read-write circuitry based on the enable signal. The third clock signal has a third pulse width that is at least greater than the first pulse width.

公开(公告)号：US20200005836A1

公开(公告)日：2020-01-02

申请号：US16024449

申请日：2018-06-29

Applicant: Arm Limited

Inventor： Lalit Gupta ,  Fakhruddin Ali Bohra ,  Jitendra Dasani ,  Shri Sagar Dwivedi ,  Vivek Nautiyal ,  Gaurav Rattan Singla

IPC: G11C7/12 ,  G11C7/18 ,  G11C7/22 ,  G11C8/14

Abstract: Various implementations described herein refer to an integrated circuit having memory circuitry having multiple banks of bitcell arrays including a first pair of bank arrays and a second pair of bank arrays. The first pair of bank arrays may have a first number of rows, and the second pair of bank arrays have a second number of rows that is different than the first number of rows. The integrated circuit may include bank multiplexer circuitry that is coupled to the first pair of bank arrays via a first channel and the second pair of bank arrays via a second channel that is separate from the first channel. The bank multiplexer circuitry may provide an output data signal from the first pair of bank arrays or the second pair of bank arrays based on a control signal.

公开(公告)号：US20190325949A1

公开(公告)日：2019-10-24

申请号：US15960482

申请日：2018-04-23

Applicant: Arm Limited

Inventor： Lalit Gupta ,  Jitendra Dasani ,  Vivek Nautiyal ,  Shri Sagar Dwivedi ,  Fakhruddin Ali Bohra

IPC: G11C11/419 ,  G11C11/412

Abstract: Various implementations described herein may refer to an integrated circuit using discharging circuitries for bit lines. In one implementation, an integrated circuit may include a memory array having memory cells, where the memory cells are arranged into columns and configured to be accessed using bit line pairs. The integrated circuit may also include discharging circuitries to selectively discharge the bit line pairs, where a respective discharging circuitry is coupled to a negative supply voltage node of a respective column of memory cells. The respective discharging circuitry may discharge a bit line pair of the respective column to a first voltage when the bit line pair is selected for a memory operation, and may discharge the bit line pair of the respective column to a second voltage when the bit line pair is not selected for a memory operation, where the second voltage is greater than the first voltage.

公开(公告)号：US10425076B2

公开(公告)日：2019-09-24

申请号：US16042949

申请日：2018-07-23

Applicant: ARM Limited

Inventor： Lalit Gupta ,  Vivek Nautiyal ,  Andy Wangkun Chen ,  Jitendra Dasani ,  Bo Zheng ,  Akshay Kumar ,  Vivek Asthana

IPC: H03K17/22 ,  G11C5/14

Abstract: Various implementations described herein are directed to a circuit. The circuit may include a memory circuit having a first latch. The circuit may include a power-on-reset circuit having a second latch coupled to the first latch. The second latch may be configured to reset the first latch to a predetermined state at power-up.

公开(公告)号：US10269416B1

公开(公告)日：2019-04-23

申请号：US15789715

申请日：2017-10-20

Applicant: ARM Limited

Inventor： Lalit Gupta ,  Jitendra Dasani ,  Vivek Nautiyal ,  Fakhruddin Ali Bohra

IPC: G11C11/417 ,  G11C11/418 ,  H01L23/528 ,  H01L27/11 ,  G11C11/412

Abstract: Various implementations described herein are directed to an integrated circuit. The integrated circuit may include dummy wordline circuitry having a dummy wordline driver coupled to multiple dummy wordline loads via a dummy wordline. The integrated circuit may include demultiplexer circuitry coupled to a first path of the dummy wordline between the dummy wordline driver and the multiple dummy wordline loads. The integrated circuit may include multiplexer circuitry coupled to a second path of the dummy wordline between the multiple dummy wordline loads and a dummy bitline load. The demultiplexer circuitry and the multiplexer circuitry may be controlled with one or more selection signals to select at least one of the multiple dummy wordline loads.

公开(公告)号：US20170317672A1

公开(公告)日：2017-11-02

申请号：US15143197

申请日：2016-04-29

Applicant: ARM Limited

Inventor： Lalit Gupta ,  Vivek Nautiyal ,  Andy Wangkun Chen ,  Jitendra Dasani ,  Bo Zheng ,  Akshay Kumar ,  Vivek Asthana

IPC: H03K17/22 ,  G11C5/14

CPC classification number: H03K17/223 ,  G11C5/148

Abstract: Various implementations described herein are directed to a circuit. The circuit may include a memory circuit having a first latch. The circuit may include a power-on-reset circuit having a second latch coupled to the first latch. The second latch may be configured to reset the first latch to a predetermined state at power-up.

公开(公告)号：US11776591B2

公开(公告)日：2023-10-03

申请号：US16584898

申请日：2019-09-26

Applicant: Arm Limited

Inventor： Lalit Gupta ,  Bo Zheng ,  El Mehdi Boujamaa ,  Fakhruddin Ali Bohra

IPC: G11C7/10 ,  G11C11/419 ,  G11C11/16 ,  G11C11/418

CPC classification number: G11C7/1015 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/418 ,  G11C11/419

Abstract: Various implementations described herein refer to a method for providing single port memory with multiple different banks having a first bank and a second bank that is different than the first bank. The method may include coupling multiple wordlines to the single port memory including coupling a first wordline to the first bank and coupling a second wordline to the second bank. The method may include performing multiple memory access operations concurrently in the single port memory.

公开(公告)号：US11588477B2

公开(公告)日：2023-02-21

申请号：US17128800

申请日：2020-12-21

Applicant: Arm Limited

Inventor： Shri Sagar Dwivedi ,  Fakhruddin Ali Bohra ,  Lalit Gupta ,  Yew Keong Chong ,  Gus Yeung

IPC: H03K5/06 ,  G06F12/0804

Abstract: Various implementations described herein are directed to an integrated circuit having clock generation circuitry that receives an input clock signal and provides a first clock signal having a first pulse width. The integrated circuit includes first pulse-stretching circuitry coupled between the clock generation circuitry and input latch control circuitry. The first pulse-stretching circuitry receives the first clock signal and provides a second clock signal to the input latch control circuitry based on an enable signal. The second clock signal has a second pulse width that is at least greater than the first pulse width. The integrated circuit may include second pulse-stretching circuitry coupled between the clock generation circuitry and read-write circuitry. The second pulse-stretching circuitry provides a third clock signal to the read-write circuitry based on the enable signal. The third clock signal has a third pulse width that is at least greater than the first pulse width.

公开(公告)号：US11574660B2

公开(公告)日：2023-02-07

申请号：US16989883

申请日：2020-08-11

Applicant: Arm Limited

Inventor： Lalit Gupta ,  Nimish Sharma ,  Hetansh Pareshbhai Shah ,  Bo Zheng

IPC: G11C7/10 ,  G11C7/06 ,  G11C16/26 ,  G11C16/10

Abstract: In a particular implementation, a circuit comprises: a memory array including a plurality of bit cells, where each of the bit cells are coupled to a respective bit path; a first multiplexer comprising a plurality of column address locations, where each of the plurality of column address locations is coupled to the memory array and corresponds to a respective bit path capacitance; and a variable capacitance circuit coupled to a reference path and configured to substantially match reference path capacitance to each of the respective bit path capacitances.

公开(公告)号：US20210111711A1

公开(公告)日：2021-04-15

申请号：US17128800

申请日：2020-12-21

Applicant: Arm Limited

Inventor： Shri Sagar Dwivedi ,  Fakhruddin Ali Bohra ,  Lalit Gupta ,  Yew Keong Chong ,  Gus Yeung

IPC: H03K5/06 ,  G06F12/0804

Abstract: Various implementations described herein are directed to an integrated circuit having clock generation circuitry that receives an input clock signal and provides a first clock signal having a first pulse width. The integrated circuit includes first pulse-stretching circuitry coupled between the clock generation circuitry and input latch control circuitry. The first pulse-stretching circuitry receives the first clock signal and provides a second clock signal to the input latch control circuitry based on an enable signal. The second clock signal has a second pulse width that is at least greater than the first pulse width. The integrated circuit may include second pulse-stretching circuitry coupled between the clock generation circuitry and read-write circuitry. The second pulse-stretching circuitry provides a third clock signal to the read-write circuitry based on the enable signal. The third clock signal has a third pulse width that is at least greater than the first pulse width.