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    Anchored data element conversion
    31.
    发明授权
    Anchored data element conversion 有权

    公开(公告)号：US10963245B2

    公开(公告)日：2021-03-30

    申请号：US16424718

    申请日：2019-05-29

    Applicant: Arm Limited

    Inventor： David Raymond Lutz ,  Neil Burgess ,  Christopher Neal Hinds ,  Nigel John Stephens

    IPC: G06F9/30 ,  H03M7/24

    Abstract: An apparatus is provided, that includes an instruction decoder responsive to an anchored-data processing instruction, to generate one or more control signals. Conversion circuitry is responsive to the one or more control signals to perform a conversion from a data value to an anchored-data select value. The conversion is based on anchor metadata indicative of a given range of significance for the anchored-data select value. Output circuitry is responsive to the one or more control signals, to write the anchored-data select value to a register.

    Arithmetic operation with shift
    32.
    发明授权
    Arithmetic operation with shift 有权

    公开(公告)号：US10678540B2

    公开(公告)日：2020-06-09

    申请号：US15973663

    申请日：2018-05-08

    Applicant: Arm Limited

    Inventor： Jacob Eapen ,  Mbou Eyole ,  Neil Burgess

    IPC: G06F9/30

    Abstract: An apparatus and method are provided for efficiently performing arithmetic operations that include at least a multiplication operation. The apparatus comprises processing circuitry to perform data processing operations, and instruction decode circuitry responsive to program instructions to generate control signals to control the processing circuitry to perform the data processing operations. In response to an arithmetic operation with shift instruction specifying performance of an arithmetic operation comprising at least a multiplication operation, and having a field which provides a programmable shift indication, the instruction decode circuitry is configured to control the processing circuitry to perform the arithmetic operation during which an intermediate value is produced, and to select a target portion of the intermediate value based on an output window determined from the programmable shift indication.

    Redundant representation of numeric value using overlap bits
    36.
    发明授权
    Redundant representation of numeric value using overlap bits 有权

    公开(公告)号：US09720646B2

    公开(公告)日：2017-08-01

    申请号：US14939175

    申请日：2015-11-12

    Applicant: ARM LIMITED

    Inventor： Neil Burgess ,  David Raymond Lutz ,  Christopher Neal Hinds

    IPC: G06F5/01 ,  G06F7/483 ,  G06F7/509 ,  G06F7/499

    CPC classification number: G06F5/012 ,  G06F7/483 ,  G06F7/49947 ,  G06F7/50 ,  G06F7/5095 ,  G06F2207/4924

    Abstract: A redundant representation is provided where an M-bit value represents a P-bit numeric value using a plurality of N-bit portions, where M>P>N. An anchor value identifies the significance of bits of each N-bit, and within a group of at least two adjacent N-bit portions, two or more overlap bits of a lower N-bit portion of the group have a same significance as two or more least significant bits of at least one upper N-bit portion of the group. A plurality of operation circuit units can perform a plurality of independent N-bit operation in parallel, each N-bit operation comprising computing a function of corresponding N-bit portions of at least two M-bit operand values having the redundant representation to generate a corresponding N-bit portion of an M-bit result value having the redundant representation. This enables fast associative processing of relatively long M-bit values in the time taken for performing an N-bit operation.

    Multi-element comparison and multi-element addition
    37.
    发明授权
    Multi-element comparison and multi-element addition 有权

    公开(公告)号：US09678715B2

    公开(公告)日：2017-06-13

    申请号：US14528326

    申请日：2014-10-30

    Applicant: ARM LIMITED

    Inventor： Neil Burgess ,  David Raymond Lutz

    IPC: G06F7/50 ,  G06F17/16 ,  G06F7/02 ,  G06F7/544 ,  G06F7/57 ,  G06F9/30 ,  G06F7/509

    CPC classification number: G06F7/50 ,  G06F7/02 ,  G06F7/509 ,  G06F7/544 ,  G06F7/57 ,  G06F9/3001 ,  G06F9/30021 ,  G06F9/30036 ,  G06F17/16

    Abstract: An apparatus 8 for performing a selectable one of multi-element comparison and multi-element addition is formed from a carry propagate adders stage 12 supplied with four non-final intermediate operands formed from the input vector, a non-final limit value selecting stage 14, which when performing a multi-element comparison serves to select, in dependence upon at least carry save values generated by the carry propagate adder, limit values that are of a larger or a smaller value of a pair of elements. A final intermediate operand forming stage 16 forms final intermediate operands from two non-final intermediate sum values from the carry propagate adders stage 12 and supplies these to a final output adder stage 18 which forms a sum of these two final intermediate operands to generate an output operand which can be either one or more candidates for limit values that will be a maximum or minimum value, or a sum value, or partial sum values in the case of a multi-element addition.

    Method and Apparatus for Converting to Enhanced Block Floating Point Format
    40.
    发明公开
    Method and Apparatus for Converting to Enhanced Block Floating Point Format 审中-公开

    公开(公告)号：US20240045653A1

    公开(公告)日：2024-02-08

    申请号：US17878277

    申请日：2022-08-01

    Applicant: Arm Limited

    Inventor： Neil Burgess ,  Sangwon Ha ,  Partha Prasun Maji

    IPC: G06F5/01

    CPC classification number: G06F5/012

    Abstract: An apparatus and method of converting data into an Enhanced Block Floating Point (EBFP) format with a shared exponent is provided. The EBFP format enables data within a wide range of values to be stored using a reduced number of bits compared with conventional floating-point or fixed-point formats. The data to be converted may be in any other format, such as fixed-point, floating-point, block floating-point or EBFP.

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