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31.发明申请公开(公告)号：US20220163576A1
公开(公告)日：2022-05-26
申请号：US17218686
申请日：2021-03-31
Applicant: Arm Limited
Inventor： Xiaoqing Xu , Zhiyao Xie , Shidhartha Das
IPC: G01R21/133 , G06F30/3308
Abstract: An integrated circuit includes a first circuit and a power meter coupled to the first circuit at selected proxy locations. The power meter includes circuitry for generating toggle data, such as signal transitions or signal levels, from signals at the proxy locations and combiner circuitry for combining the toggle data in a first time window with a set of weight value to produce a measure of power usage in the first circuit. The proxy locations and weight values are selected automatically based on simulated or emulated signals from a larger set of locations in the first circuit and associated power usage in the first circuit.
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公开(公告)号：US11232236B2
公开(公告)日：2022-01-25
申请号：US17048521
申请日：2019-04-18
Applicant: Arm Limited
Inventor： Hugo John Martin Vincent , Shidhartha Das , Milosch Meriac , Vasileios Tenentes
IPC: H04L29/06 , G06F21/75 , G01R19/165 , G01R31/08 , G06F1/28 , G06F21/44 , H04L9/00 , H04L9/08 , H04L9/32 , G01R19/00 , G01R29/26
Abstract: A method and authenticator for authenticating a device in a system using the electrical properties of the device is disclosed. Embodiments of the disclosure enable authentication by receiving a plurality of input seed values from a requestor. For each input seed value, load stimuli are generated to produce an electrical load sequence on a power delivery network powering at least part of the system. Noise induced in the power delivery network is measured in response to the electrical load sequence using one or more sensors located on the power delivery network. Based on the measured noise, a dynamic response property (magnitude and phase response as a function of frequency) of the power delivery network corresponding to a respective input seed value can be determined and returned to the requestor.
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公开(公告)号：US10964386B2
公开(公告)日：2021-03-30
申请号：US16496820
申请日：2018-03-26
Applicant: Arm Limited
Inventor： Wei Wang , Shidhartha Das
Abstract: There is provided a system comprising: a storage device having a storage portion comprising a plurality of bitcells coupled to respective first signal lines and second signal lines and control logic to alter a memory state of the plurality of bitcells via the first signal lines and second signal lines; a memory controller coupled to the storage device to transmit one or more initialisation signals to the storage device; wherein the storage device is to initialise the storage portion over a clock cycle in response to the one or more initialisation signals.
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公开(公告)号：US20210064379A1
公开(公告)日：2021-03-04
申请号：US16556101
申请日：2019-08-29
Applicant: Arm Limited
Inventor： Matthew Mattina , Shidhartha Das , Glen Arnold Rosendale , Fernando Garcia Redondo
Abstract: A method and architecture for performing multiply-accumulate operations in a neural network is disclosed. The architecture includes a crossbar having a plurality of non-volatile memory elements. A plurality of input activations is applied to the crossbar, which are then summed by binary weight encoding a plurality of the non-volatile memory elements to connect the input activations to weight values. At least one of the plurality of non-volatile memory elements is then precision programmed.
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公开(公告)号：US20200286557A1
公开(公告)日：2020-09-10
申请号：US16496820
申请日：2018-03-26
Applicant: Arm Limited
Inventor： Wei Wang , Shidhartha Das
IPC: G11C13/00
Abstract: There is provided a system comprising: a storage device having a storage portion comprising a plurality of bitcells coupled to respective first signal lines and second signal lines and control logic to alter a memory state of the plurality of bitcells via the first signal lines and second signal lines; a memory controller coupled to the storage device to transmit one or more initialisation signals to the storage device; wherein the storage device is to initialise the storage portion over a clock cycle in response to the one or more initialisation signals.
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Patent Agency Ranking
36.发明申请公开(公告)号：US20200251152A1
公开(公告)日：2020-08-06
申请号：US16833154
申请日：2020-03-27
Applicant: Arm Limited
Inventor： Mudit Bhargava , Shidhartha Das , George McNeil Lattimore , Brian Tracy Cline
Abstract: Disclosed are methods, systems and devices for operation of memory device. In one aspect, volatile memory bitcells and non-volatile memory bitcells may be integrated to facilitate copying of memory states between the volatile and non-volatile memory bitcells.
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公开(公告)号：US10447412B2
公开(公告)日：2019-10-15
申请号：US15577487
申请日：2016-04-15
Applicant: ARM LIMITED
Inventor： Paul Nicholas Whatmough , George Smart , Shidhartha Das , David Michael Bull
IPC: H04B7/24 , H04B13/00 , H04B1/3827
Abstract: A device comprises a coupling configured to couple signals to and from a communications path including at least a part of a human or animal body; a data transmitter coupled to the coupling and configured to transmit, from time to time, a data signal of at least a predetermined temporal duration via the communications path; and a data receiver coupled to the coupling and configured to detect the presence of a signal on the communications path at sets of one or more successive detection instances disposed between successive transmissions of the data signal by the data transmitter, the data receiver being configured so that the successive detection instances of a set are temporally separated by no more than the predetermined temporal duration; the device being configured to initiate a processing operation in response to a detection by the data receiver of the presence of a signal on the communications path.
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公开(公告)号：US09933466B2
公开(公告)日：2018-04-03
申请号：US15172101
申请日：2016-06-02
Applicant: ARM Limited
Inventor： Paul Nicholas Whatmough , Shidhartha Das , David Michael Bull
Abstract: An apparatus and method are provided for detecting a resonant frequency giving rise to an impedance peak in a power delivery network used to provide a supply voltage. The apparatus includes resonant frequency detection circuitry that comprises test frequency control circuitry and a loading circuit. The test frequency control circuitry is arranged to generate control signals to indicate a sequence of test frequencies. A loading circuit is controlled by the control signals and operates from the supply voltage. In particular, in response to each test frequency indicated by the control signals, the loading circuit draws a duty-cycled current load through the power delivery network at that test frequency. Operation of the loading circuit produces a measurable property whose value varies in dependence on the supply voltage, thus enabling the resonant frequency to be determined from a variation in the value of that measurable property.
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公开(公告)号：US08862935B2
公开(公告)日：2014-10-14
申请号：US14143352
申请日：2013-12-30
Applicant: ARM Limited
Inventor： Shidhartha Das , David Michael Bull , Emre Ozer
IPC: G06F11/00 , G06F11/07 , G06F11/16 , G06F11/10 , G01R31/3181
CPC classification number: G06F11/0793 , G01R31/31816 , G06F11/1076 , G06F11/1608
Abstract: An integrated circuit is provided with error detection circuitry and error repair circuitry. Error tolerance circuitry is responsive to a control parameter to selectively disable the error repair circuitry. The control parameter is dependent on the processing performed within the circuit. For example, the control parameter may be generated in dependence upon the program instruction being executed, the output signal value which is in error, the previous behavior of the circuit or in other ways.
Abstract translation: 集成电路具有错误检测电路和错误修复电路。 误差容限电路响应于控制参数来选择性地禁用错误修复电路。 控制参数取决于电路内执行的处理。 例如，控制参数可以根据执行的程序指令，错误的输出信号值，电路的先前行为或其他方式来生成。
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公开(公告)号：US12118088B2
公开(公告)日：2024-10-15
申请号：US16855716
申请日：2020-04-22
Applicant: Arm Limited
Inventor： Subbayya Chowdary Yanamadala , Jeremy Patrick Dubeuf , Carl Wayne Vineyard , Matthias Lothar Boettcher , Hugo John Martin Vincent , Shidhartha Das
CPC classification number: G06F21/566 , G06F9/54 , G06F21/72 , G06F21/85 , G06F2221/034
Abstract: A moderator system that can receive outputs of various stages of the security analytic framework and can receive input from external sources to provide information about emerging styles of attacks. One or more models/behavioral profiles can be curated by the moderator system, and the moderator system can provide updates to components of the security analytics framework.
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