公开(公告)号：US20240264841A1

公开(公告)日：2024-08-08

申请号：US18107139

申请日：2023-02-08

Applicant: Arm Limited

Inventor： Glen Andrew HARRIS ,  Alexander Cole SHULYAK ,  . ABHISHEK RAJA ,  Bipin Prasad HEREMAGALUR RAMAPRASAD ,  William Elton BURKY ,  Li MA ,  Michael David ACHENBACH ,  Nicholas Andrew PLANTE ,  Yasuo ISHII

IPC: G06F9/38

CPC classification number: G06F9/3856 ,  G06F9/3861

Abstract: There is provided an apparatus, method and medium. The apparatus comprises processing circuitry to process instructions and a reorder buffer identifying a plurality of entries having state information associated with execution of one or more of the instructions. The apparatus comprises allocation circuitry to allocate entries in the reorder buffer, and to allocate at least one compressed entry corresponding to a plurality of the instructions. The apparatus comprises memory access circuitry responsive to an address associated with a memory access instruction corresponding to access-sensitive memory and the memory access instruction corresponding to the compressed entry, to trigger a reallocation procedure comprising flushing the memory access instruction and triggering reallocation of the memory access instruction without the compression. The allocation circuitry is responsive to a frequency of occurrence of memory access instructions addressing the access-sensitive memory meeting a predetermined condition, to suppress the compression whilst the predetermined condition is met.

公开(公告)号：US20240111535A1

公开(公告)日：2024-04-04

申请号：US17959556

申请日：2022-10-04

Applicant: Arm Limited

Inventor： William Elton BURKY ,  Nicholas Andrew PLANTE ,  Alexander Cole SHULYAK ,  Joshua David KNEBEL ,  Yasuo ISHII

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30145 ,  G06F9/30181 ,  G06F9/3855

Abstract: A data processing apparatus includes detection circuitry that detects a parent instruction and a child instruction from a stream of instructions. The parent instruction references a destination register that is referenced as a source register by the child instruction. Adjustment circuitry then adjusts the child instruction to produce an adjusted child instruction whose behaviour is logically equivalent to a behaviour of executing the parent instruction followed by the child instruction.

公开(公告)号：US20240095034A1

公开(公告)日：2024-03-21

申请号：US17949874

申请日：2022-09-21

Applicant: Arm Limited

Inventor： James David DUNDAS ,  Yasuo ISHII ,  Michael Brian SCHINZLER

IPC: G06F9/38

CPC classification number: G06F9/3838 ,  G06F9/3861

Abstract: A data processing apparatus includes control flow prediction circuitry that generates a control flow prediction in respect of a group of one or more instructions. Storage circuitry used by the control flow prediction circuitry stores data in association with groups of instructions used to generate the control flow prediction for each of the groups of instructions. Control flow prediction update circuitry inserts new data into the storage circuitry in association with a new group of one or more instructions in dependence on one or more conditions being met when a miss occurs for the group of one or more instructions in the storage circuitry.

公开(公告)号：US20240078012A1

公开(公告)日：2024-03-07

申请号：US17903293

申请日：2022-09-06

Applicant: Arm Limited

Inventor： ABHISHEK RAJA ,  Yasuo ISHII

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0656 ,  G06F3/0673

Abstract: There is provided an apparatus, method and medium. The apparatus comprises a store buffer to store a plurality of store requests, where each of the plurality of store requests identifies a storage address and a data item to be transferred to storage beginning at the storage address, where the data item comprises a predetermined number of bytes. The apparatus is responsive to a memory access instruction indicating a store operation specifying storage of N data items, to determine an address allocation order of N consecutive store requests based on a copy direction hint indicative of whether the memory access instruction is one of a sequence of memory access instructions each identifying one of a sequence of sequentially decreasing addresses, and to allocate the N consecutive store requests to the store buffer in the address allocation order.

公开(公告)号：US20240020237A1

公开(公告)日：2024-01-18

申请号：US17864625

申请日：2022-07-14

Applicant: Arm Limited

Inventor： Yasuo ISHII ,  Jungsoo KIM ,  James David DUNDAS ,  . ABHISHEK RAJA

IPC: G06F12/0897

CPC classification number: G06F12/0897 ,  G06F2212/60

Abstract: There is provided a data processing apparatus in which receive circuitry receives a result signal from a lower level cache and a higher level cache in respect of a first instruction block. The lower level cache and the higher level cache are arranged hierarchically and transmit circuitry transmits, to the higher level cache, a query for the result signal. In response to the result signal originating from the higher level cache containing requested data, the transmit circuitry transmits a further query to the higher level cache for a subsequent instruction block at an earlier time than the further query is transmitted to the higher level cache when the result signal containing the requested data originates from the lower level cache.

公开(公告)号：US20230385066A1

公开(公告)日：2023-11-30

申请号：US17752060

申请日：2022-05-24

Applicant: Arm Limited

Inventor： Houdhaifa BOUZGUARROU ,  Michael Brian SCHINZLER ,  Yasuo ISHII ,  Jatin BHARTIA ,  Sumanth CHENGAD RAGHU

IPC: G06F9/38 ,  G06F1/03

CPC classification number: G06F9/3848 ,  G06F9/3844 ,  G06F9/3806 ,  G06F1/03

Abstract: A first type of prediction, for controlling execution of at least one instruction by processing circuitry, is based at least on a first prediction table storing prediction information looked up based on at least a first portion of branch history information stored in branch history storage corresponding to a first predetermined number of branches. In response to detecting an execution state switch of the processing circuitry from a first execution state to a second, more privileged, execution state, use of the first prediction table for determining the first type of prediction is disabled. In response to detecting that a number of branches causing an update to the branch history storage since the execution state switch is greater than or equal to the first predetermined number, use of the first prediction table in determining the first type of prediction is re-enabled.

公开(公告)号：US20230229596A1

公开(公告)日：2023-07-20

申请号：US17579842

申请日：2022-01-20

Applicant: Arm Limited

Inventor： Alexander Cole SHULYAK ,  Balaji VIJAYAN ,  Karthik SUNDARAM ,  Yasuo ISHII ,  Joseph Michael PUSDESRIS

IPC: G06F12/0862

CPC classification number: G06F12/0862 ,  G06F2212/1024 ,  G06F2212/602

Abstract: Indirect prefetch circuitry initiates a producer prefetch requesting return of producer data having a producer address and at least one consumer prefetch to request prefetching of consumer data having a consumer address derived from the producer data. A producer prefetch filter table stores producer filter entries indicative of previous producer addresses of previous producer prefetches. Initiation of a requested producer prefetch for producer data having a requested producer address is suppressed when a lookup of the producer prefetch filter table determines that the requested producer address hits against a producer filter entry of the table. The lookup of the producer prefetch filter table for the requested producer address depends on a subset of bits of the requested producer address including at least one bit which distinguishes different chunks of data within a same cache line.

公开(公告)号：US20230214223A1

公开(公告)日：2023-07-06

申请号：US17569157

申请日：2022-01-05

Applicant: Arm Limited

Inventor： Yasuo ISHII ,  Michael David ACHENBACH ,  David Gum LIM ,  ABHISHEK RAJA

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3855 ,  G06F9/3016

Abstract: There is provided a data processing apparatus comprising decode circuitry responsive to receipt of a block of instructions to generate control signals indicative of each of the block of instructions, and to analyse the block of instructions to detect a potential hazard instruction. The data processing apparatus is provided with decode circuitry to encode information indicative of a clean restart point into the control signals associated with the potential hazard instruction. The data processing apparatus is provided with data processing circuitry to perform out-of-order execution of at least some of the block of instructions, and control circuitry responsive to a determination, at execution of the potential hazard instruction, that data values used as operands for the potential hazard instruction have been modified by out-of-order execution of a subsequent instruction, to restart execution from the clean restart point and to flush held data values from the data processing circuitry.

公开(公告)号：US20220107898A1

公开(公告)日：2022-04-07

申请号：US17060624

申请日：2020-10-01

Applicant: Arm Limited

Inventor： Yasuo ISHII ,  James David DUNDAS ,  Chang Joo LEE ,  Muhammad Umar FAROOQ

IPC: G06F12/0864 ,  G06F12/0811 ,  G06F12/0873 ,  G06F12/121

Abstract: An apparatus comprises first-level and second-level set-associative caches each comprising the same number of sets of cache entries. Indexing circuitry generates, based on a lookup address, a set index identifying which set of the first-level set-associative cache or the second-level set-associative cache is a selected set of cache entries to be looked up for information associated with the lookup address. The indexing circuitry generates the set index using an indexing scheme which maps the lookup address to the same set index for both the first-level set-associative cache and the second-level set-associative cache. This can make migration of cached information between the cache levels more efficient, which can be particularly useful for caches with high access frequency, such as branch target buffers for a branch predictor.

公开(公告)号：US20200310812A1

公开(公告)日：2020-10-01

申请号：US16364570

申请日：2019-03-26

Applicant: Arm Limited

Inventor： Yasuo ISHII ,  Muhammad Umar FAROOQ

IPC: G06F9/38 ,  G06F9/30

Abstract: An apparatus and method are provided for making predictions for instruction flow changing instructions. The apparatus has a fetch queue that identifies a sequence of instructions to be fetched for execution by execution circuitry, and prediction circuitry for making predictions in respect of instruction flow changing instructions, and for controlling which instructions are identified in the fetch queue in dependence on the predictions. The prediction circuitry is arranged, during each prediction iteration, to make a prediction for a predict block comprising a sequence of M instruction addresses, in order to identify whether that predict block contains the instruction address for an instruction flow changing instruction that is predicted as taken. During each prediction iteration, the prediction circuitry is arranged by default to access a prediction storage in order to produce prediction information for instructions associated with a specified block of instruction addresses (including at least the predict block being considered), and to use that prediction information to make the prediction for the predict block. Buffer storage is used to retain the prediction information obtained from the prediction storage during one or more previous prediction iterations, and detection circuitry is used to detect when a current predict block being considered during a current prediction iteration comprises one or more instruction addresses for which the associated prediction information is retained in the buffer storage. In that event, the above default behaviour is not adopted, and an override condition is triggered to cause the prediction information for those one or more instruction addresses to be obtained from the buffer storage rather than from the prediction storage, giving rise to a power saving.