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    GLUCAGON ANTAGONISTS
    31.
    发明申请
    GLUCAGON ANTAGONISTS 有权

    公开(公告)号：US20120122783A1

    公开(公告)日：2012-05-17

    申请号：US12739342

    申请日：2008-10-23

    Applicant: Richard D. Dimarchi ,  Bin Yang

    Inventor： Richard D. Dimarchi ,  Bin Yang

    IPC: A61K38/26 ,  A61P3/10 ,  C07K14/605

    CPC classification number: C07K14/605 ,  A61K38/00

    Abstract: Glucagon antagonists are provided which comprise amino acid substitutions and/or chemical modifications to glucagon sequence. In one embodiment, the glucagon antagonists comprise a native glucagon peptide that has been modified by the deletion of the first two to five amino acid residues from the N-terminus and (i) an amino acid substitution at position 9 (according to the numbering of native glucagon) or (ii) substitution of the Phe at position 6 (according to the numbering of native glucagon) with phenyl lactic acid (PLA). In another embodiment, the glucagon antagonists comprise the structure A-B-C as described herein, wherein A is PLA, an oxy derivative thereof, or a peptide of 2-6 amino acids in which two consecutive amino acids of the peptide are linked via an ester or ether bond.

    Abstract translation: 提供了包含对胰高血糖素序列的氨基酸取代和/或化学修饰的胰高血糖素拮抗剂。 在一个实施方案中，胰高血糖素拮抗剂包含通过从N-末端缺失前两个至五个氨基酸残基而修饰的天然胰高血糖素肽，以及（i）在第9位的氨基酸取代（根据 天然胰高血糖素）或（ii）用苯基乳酸（PLA）取代第6位的Phe（根据天然胰高血糖素的编号）。 在另一个实施方案中，胰高血糖素拮抗剂包含如本文所述的结构ABC，其中A是PLA，其氧衍生物或2-6个氨基酸的肽，其中肽的两个连续氨基酸经由酯或醚连接 键。

    SEMICONDUCTOR DEVICE WITH REDUCED JUNCTION LEAKAGE AND AN ASSOCIATED METHOD OF FORMING SUCH A SEMICONDUCTOR DEVICE
    32.
    发明申请
    SEMICONDUCTOR DEVICE WITH REDUCED JUNCTION LEAKAGE AND AN ASSOCIATED METHOD OF FORMING SUCH A SEMICONDUCTOR DEVICE 失效
    具有降低接合泄漏的半导体器件和形成这种半导体器件的相关方法

    公开(公告)号：US20120098042A1

    公开(公告)日：2012-04-26

    申请号：US12911186

    申请日：2010-10-25

    Applicant: Ming Cai ,  Christian Lavoie ,  Ahmet S. Ozcan ,  Bin Yang ,  Zhen Zhang

    Inventor： Ming Cai ,  Christian Lavoie ,  Ahmet S. Ozcan ,  Bin Yang ,  Zhen Zhang

    IPC: H01L29/78 ,  H01L21/336 ,  H01L21/04

    CPC classification number: H01L21/2257 ,  H01L21/28512 ,  H01L21/28518 ,  H01L29/665 ,  H01L29/66643

    Abstract: Disclosed is a semiconductor device having a p-n junction with reduced junction leakage in the presence of metal silicide defects that extend to the junction and a method of forming the device. Specifically, a semiconductor layer having a p-n junction is formed. A metal silicide layer is formed on the semiconductor layer and a dopant is implanted into the metal silicide layer. An anneal process is performed causing the dopant to migrate toward the metal silicide-semiconductor layer interface such that the peak concentration of the dopant will be within a portion of the metal silicide layer bordering the metal silicide-semiconductor layer interface and encompassing the defects. As a result, the silicide to silicon contact is effectively engineered to increase the Schottky barrier height at the defect, which in turn drastically reduces any leakage that would otherwise occur, when the p-n junction is in reverse polarity.

    Abstract translation: 公开了一种具有p-n结的半导体器件，其在存在延伸到结的金属硅化物缺陷的情况下具有减少的结漏电以及形成器件的方法。 具体地说，形成具有p-n结的半导体层。 在半导体层上形成金属硅化物层，并且将掺杂剂注入到金属硅化物层中。 执行退火处理，使掺杂剂朝向金属硅化物半导体层界面迁移，使得掺杂剂的峰值浓度将在金属硅化物层的与金属硅化物半导体层界面接壤并包围缺陷的部分内。 结果，硅化物与硅接触被有效地设计以增加缺陷处的肖特基势垒高度，这反过来大大降低了当p-n结处于相反极性时将会发生的任何泄漏。

    MEMS THREE-AXIS ACCELEROMETER
    35.
    发明申请
    MEMS THREE-AXIS ACCELEROMETER 审中-公开
    MEMS三轴加速度计

    公开(公告)号：US20110303010A1

    公开(公告)日：2011-12-15

    申请号：US13016172

    申请日：2011-01-28

    Applicant: Bin Yang

    Inventor： Bin Yang

    IPC: G01P15/125

    CPC classification number: G01P15/125 ,  G01P15/18 ,  G01P2015/082 ,  G01P2015/0837

    Abstract: A MEMS three-axis accelerometer includes a silicon substrate, a first electrode and a second electrode etched in the same silicon substrate. The first electrode is constituted by a mobile mass fitted with a plurality of mobile fingers extending laterally. The second electrode is composed of two conductive parts located on two opposite sides of the mobile mass. Each conductive part comprises a plurality of fixed fingers formed parallel to the mobile fingers. Each mobile finger is positioned between two contiguous fixed fingers to cooperatively form a microstructure with interdigital combs. The mobile mass is connected to the substrate by a spring.

    Abstract translation: MEMS三轴加速度计包括硅衬底，在同一硅衬底中蚀刻的第一电极和第二电极。 第一电极由装配有横向延伸的多个可移动指状物的移动体构成。 第二电极由位于移动体的两个相对侧上的两个导电部件组成。 每个导电部分包括与移动手指平行的多个固定指状物。 每个可移动手指定位在两个连续的固定指状物之间，以协同地形成具有叉指梳的微结构。 移动块通过弹簧连接到基板。

    METAL GATE FILL BY OPTIMIZING ETCH IN SACRIFICIAL GATE PROFILE
    36.
    发明申请
    METAL GATE FILL BY OPTIMIZING ETCH IN SACRIFICIAL GATE PROFILE 审中-公开
    金属门盖通过优化浇口配置文件进行优化

    公开(公告)号：US20110241118A1

    公开(公告)日：2011-10-06

    申请号：US12750340

    申请日：2010-03-30

    Applicant: Man Fai Ng ,  Bin Yang

    Inventor： Man Fai Ng ,  Bin Yang

    IPC: H01L29/423 ,  H01L21/28 ,  H01L29/78

    CPC classification number: H01L21/28114 ,  H01L29/42376 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833

    Abstract: A high-k metal gate electrode is formed with reduced gate voids. An embodiment includes forming a replaceable gate electrode, for example of amorphous silicon, having a top surface and a bottom surface, the top surface being larger than the bottom surface, removing the replaceable gate electrode, forming a cavity having a top opening larger than a bottom opening, and filling the cavity with metal. The larger top surface may be formed by etching the bottom portion of the amorphous silicon at greater temperature than the top portion, or by doping the top and bottom portions of the amorphous silicon differently such that the bottom has a greater lateral etch rate than the top.

    Abstract translation: 形成具有减小的栅极空隙的高k金属栅电极。 一个实施例包括形成可替换的栅电极，例如具有顶表面和底表面的非晶硅，顶表面大于底表面，去除可更换的栅电极，形成具有大于 底部开口，并用金属填充空腔。 可以通过在比顶部更高的温度下蚀刻非晶硅的底部，或者通过不同地掺杂非晶硅的顶部和底部来形成较大的顶表面，使得底部具有比顶部更大的侧向蚀刻速率 。

    Method for forming a protection layer over metal semiconductor contact and structure formed thereon
    37.
    发明授权
    Method for forming a protection layer over metal semiconductor contact and structure formed thereon 失效
    用于在金属半导体接触和其上形成的结构上形成保护层的方法

    公开(公告)号：US08030154B1

    公开(公告)日：2011-10-04

    申请号：US12849223

    申请日：2010-08-03

    Applicant: Ahmet S. Ozcan ,  Christian Lavoie ,  Zhen Zhang ,  Bin Yang

    Inventor： Ahmet S. Ozcan ,  Christian Lavoie ,  Zhen Zhang ,  Bin Yang

    IPC: H01L21/8238

    CPC classification number: H01L21/823807 ,  H01L21/823864 ,  H01L29/7843

    Abstract: In one embodiment, a method of forming a semiconductor device is provided that includes providing a gate structure on a semiconductor substrate. Sidewall spacers may be formed adjacent to the gate structure. A metal semiconductor alloy may be formed on the upper surface of the gate structure and on an exposed surface of the semiconductor substrate that is adjacent to the gate structure. An upper surface of the metal semiconductor alloy is converted to an oxygen-containing protective layer. The sidewall spacers are removed using an etch that is selective to the oxygen-containing protective layer. A strain-inducing layer is formed over the gate structure and the semiconductor surface, in which at least a portion of the strain-inducing layer is in direct contact with the sidewall surface of the gate structure. In another embodiment, the oxygen-containing protective layer of the metal semiconductor alloy is provided by a two stage annealing process.

    Abstract translation: 在一个实施例中，提供了一种形成半导体器件的方法，其包括在半导体衬底上提供栅极结构。 侧壁间隔件可以与栅极结构相邻地形成。 可以在栅极结构的上表面和与栅极结构相邻的半导体衬底的暴露表面上形成金属半导体合金。 将金属半导体合金的上表面转化为含氧保护层。 使用对含氧保护层具有选择性的蚀刻来去除侧壁间隔物。 应变诱导层形成在栅极结构和半导体表面上，其中应变诱导层的至少一部分与栅极结构的侧壁表面直接接触。 在另一个实施方案中，金属半导体合金的含氧保护层通过两阶段退火工艺提供。

    METHOD AND DEVICE FOR PRINTING IMAGE
    39.
    发明申请
    METHOD AND DEVICE FOR PRINTING IMAGE 失效
    打印图像的方法和装置

    公开(公告)号：US20110085002A1

    公开(公告)日：2011-04-14

    申请号：US12920267

    申请日：2009-02-27

    Applicant: Jinghua Shen ,  Yapeng Chen ,  Bin Yang ,  Lidong Wang

    Inventor： Jinghua Shen ,  Yapeng Chen ,  Bin Yang ,  Lidong Wang

    IPC: B41J29/38 ,  G06T5/00

    CPC classification number: G06K15/02 ,  H04N1/40068

    Abstract: Disclosed is a method for printing an image, comprising a step of rasterizing an image to be printed in view of a first resolution to generate a first data bitmap; a step of splitting the first data bitmap according to a ratio of the first resolution to a second resolution to generate second data bitmaps; and a step of outputting the second data bitmaps to a printer with the second resolution for printing. Disclosed is also a device for printing images. The method and device for printing an image may solve the problem in the prior art that the definition of an image printed from a printer is too low and improve the definition of an image printed from a printer.

    Abstract translation: 公开了一种打印图像的方法，包括：根据第一分辨率光栅化要打印的图像以生成第一数据位图的步骤; 根据第一分辨率与第二分辨率的比率分割第一数据位图以产生第二数据位图的步骤; 以及将第二数据位图输出到具有用于打印的第二分辨率的打印机的步骤。 公开了一种用于打印图像的装置。 用于打印图像的方法和设备可以解决现有技术中从打印机打印的图像的定义太低并且提高从打印机打印的图像的定义的问题。

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