Fan assembly for a processing unit case
    31.
    发明授权
    Fan assembly for a processing unit case 失效
    风扇组件用于处理单元外壳

    公开(公告)号:US5984634A

    公开(公告)日:1999-11-16

    申请号:US984343

    申请日:1997-12-03

    摘要: A cabinet having a plurality of compartments adapted to have disposed in a corresponding one thereof one of a plurality of processing unit modules. Each one of the modules includes a case. The case has a motherboard mounting surface adapted to have mounted thereto one of a plurality of differently configured motherboards, each one of the differently configured motherboards having a different arrangement of a CPU, main memory and I/O adapted cards. The case also has a bulkhead mounting surface adapted to have mounted thereto one of a plurality of differently configured I/O bulkheads, each one of the differently configured bulkheads being configured for a corresponding one of the differently configured motherboards. The case has a fan mounting surface adapted to have mounted thereto one of a plurality of differently configured fan assemblies, each one of the differently configured fan assemblies being configured for a corresponding one of the differently configured motherboards. The case is provided having a motherboard mounting surface adapted to have mounted thereto a CPU, main memory and an I/O adapter card. The I/O adapter card has a front lower edge adapted for plugging into the motherboard. A cover is adapted for mounting to the case over the motherboard. The cover has an anti-vibration member adapted to engage a rear upper edge of the I/O adapter card and maintain the I/O adapter card securely plugged into the motherboard when the cover is mounted to the case.

    摘要翻译: 一种具有多个隔室的柜体,其适于在多个处理单元模块中的一个处于相应的一个处置单元模块中。 每个模块包括一个壳体。 壳体具有适于安装到多个不同配置的主板之一的主板安装表面,每个不同配置的主板具有CPU,主存储器和I / O适配卡的不同布置。 壳体还具有适于安装到多个不同配置的I / O舱壁中的一个的隔板安装表面,每个不同配置的隔板被配置用于相应的一个不同配置的主板。 壳体具有风扇安装表面,其适于安装到多个不同构造的风扇组件中的一个,不同配置的风扇组件中的每一个被配置用于相应的一个不同配置的主板。 提供了具有适于安装有CPU,主存储器和I / O适配器卡的主板安装表面的情况。 I / O适配卡具有适合插入主板的前下边缘。 适用于安装在主板上的外壳上的盖子。 所述盖具有适于接合所述I / O适配器卡的后上边缘的防振构件,并且当所述盖安装到所述壳体时,将所述I / O适配器卡牢固地插入所述主板。

    Backplane having strip transmission line ethernet bus

    公开(公告)号:US5971804A

    公开(公告)日:1999-10-26

    申请号:US885381

    申请日:1997-06-30

    摘要: A data server having a plurality of hot replaceable processing unit modules. Each module includes a motherboard having plugged therein: a CPU; a main memory; an I/O adapter card, and an interconnect printed board, electrically connected to the motherboard. A backplane has a first connector adapted for coupling to a DC power supply. The interconnect printed circuit board has a DC to DC converter connected to a second connector adapted to mate with the first connector to enable the processing unit module to be hot plugged into, or removed from, the backplane. The backplane has formed thereon a strip transmission line adapted to provide an Ethernet bus for interconnecting a plurality of the modules. A cable management system for a cabinet used to house the module includes at least one vertically extending channel disposed in the cabinet and a fastener adapted to open and enable the a cable to be inserted into the channel and close to retain such cable within the channel. A chassis having a plurality of shelves for supporting electrical modules with a partitioning member adapted for removable insertion onto one of the shelves to accommodate modules with different widths. An I/O adapter card mounting plate, with captive hardware, adapted for securing an array of I/O adapted cards, and honey-combed I/O adapter card filler plate to a case. A method for booting operating system software into a main memory of a processing unit.

    Dual power bus data storage system
    40.
    发明授权
    Dual power bus data storage system 有权
    双电源总线数据存储系统

    公开(公告)号:US07062620B1

    公开(公告)日:2006-06-13

    申请号:US10331423

    申请日:2002-12-30

    IPC分类号: G00F12/00

    CPC分类号: G06F12/0866

    摘要: A data storage interface for coupling data between processors and a bank of disk. The interface includes a plurality of first directors coupled to the processors and a plurality of second directors coupled to the bank of disk drives. A cache memory is coupled between the plurality of first directors and the plurality of second directors. The interface includes a pair of independent power busses. At least one of the first or second directors is coupled to the pair of independent power busses. One portion of the disk drives in the bank is connected to only a first one of the pair of power buses and a different portion of the disk drives is connected to only the other one of the pair of power buses. A power circuit includes a pair of input terminals, each one being electrically connected to a corresponding one of the pair of independent power busses. The circuit includes an output terminal. A pair of switching transistor sections is provided. The transistor switching sections is serially connected between a corresponding one of the pair of input terminals and the output terminal. A logic network is provided for operating the switching sections to prevent current passing into one of the pair of input terminals from one of the power busses from passing into the other one of the power buses. The logic section operates the switching sections to prevent current from one of the pair of power buses to the one of the input terminals connected thereto from exceeding a predetermined value, and operates the switching sections to prevent a difference between a voltage at one of the input terminals and a voltage at the other one of the input terminals from exceeding a predetermined value.

    摘要翻译: 一种数据存储接口,用于在处理器和一组磁盘之间耦合数据。 接口包括耦合到处理器的多个第一引导器和耦合到盘驱动器组的多个第二引导器。 高速缓冲存储器耦合在多个第一引导器和多个第二引导器之间。 该接口包括一对独立的电力总线。 第一或第二导体中的至少一个耦合到一对独立电力总线。 组中的磁盘驱动器的一部分仅连接到一对电源总线中的第一个,并且磁盘驱动器的不同部分仅连接到该对电源总线中的另一个。 电源电路包括一对输入端子,每一个输入端子电连接到该对独立电力总线中相应的一个。 该电路包括输出端子。 提供一对开关晶体管部分。 晶体管开关部串联连接在一对输入端子和输出端子的对应的一个。 提供了一个逻辑网络,用于操作开关部分,以防止电流从一个电力总线进入一对输入端子中的一个,以进入另一个电力总线。 逻辑部分操作切换部分,以防止从一对电力总线中的一个到连接到其上的一个输入端子的电流超过预定值,并且操作开关部分以防止输入之一处的电压之间的差 端子和另一个输入端子处的电压超过预定值。