公开(公告)号：US20140006233A1

公开(公告)日：2014-01-02

申请号：US13535854

申请日：2012-06-28

申请人： Kathrin Hamburger ,  Elena Renkewitsch ,  Andrea Hahn ,  Michael Hoffmann ,  Thomas Breitling ,  Joachim Liebler ,  Kai-Michael Roesner ,  Alexander Fuerbach ,  Thomas Hoffmann ,  Peter Illg ,  Jutta Kaemper ,  Dietmar Kaiser ,  Enrico Mayer ,  Thomas Schachner ,  Michael Schmidt ,  Martin Walew ,  Dirk Henrich

发明人： Kathrin Hamburger ,  Elena Renkewitsch ,  Andrea Hahn ,  Michael Hoffmann ,  Thomas Breitling ,  Joachim Liebler ,  Kai-Michael Roesner ,  Alexander Fuerbach ,  Thomas Hoffmann ,  Peter Illg ,  Jutta Kaemper ,  Dietmar Kaiser ,  Enrico Mayer ,  Thomas Schachner ,  Michael Schmidt ,  Martin Walew ,  Dirk Henrich

IPC分类号： G06Q40/00

CPC分类号： G06Q40/00 ,  G06Q40/12

摘要： A business object model, which reflects data that is used during a given business transaction, is utilized to generate interfaces. This business object model facilitates commercial transactions by providing consistent interfaces that are suitable for use across industries, across businesses, and across different departments within a business during a business transaction. In some operations, software creates, updates, or otherwise processes information related to a financial accounting view of cost object expense list and a financials view of contract business object.

摘要翻译： 用于反映在给定业务事务期间使用的数据的业务对象模型被用于生成接口。 该业务对象模型通过提供一致的接口来促进商业交易，该接口适合于在业务交易期间跨业务，跨企业以及业务中的不同部门使用。 在一些操作中，软件创建，更新或以其他方式处理与成本对象费用列表的财务会计视图相关的信息以及合同业务对象的财务视图。

公开(公告)号：US08303309B2

公开(公告)日：2012-11-06

申请号：US12172027

申请日：2008-07-11

申请人： Thomas Hoffmann ,  Michael K. Russell

发明人： Thomas Hoffmann ,  Michael K. Russell

IPC分类号： G09B21/00

CPC分类号： G09B7/06 ,  G09B19/00 ,  G09B21/00

摘要： In an exemplary embodiment, a computer-implemented method for implementing a test delivery system is provided. The method includes implementing a plurality of interoperable accommodation and accessibility tools, and providing an interface to the test with the plurality of interoperable accommodation and accessibility tools provided on the interface. The method also includes receiving one or more tool settings for a test-taker specifying one or more permitted tools in the plurality of interoperable accommodation and accessibility tools, and customizing the interface based on the one or more tool settings to allow the test-taker access to the one or more permitted tools during the test. The method further includes allowing the test-taker to activate or deactivate each of the one or more permitted tools.

摘要翻译： 在示例性实施例中，提供了一种用于实现测试传递系统的计算机实现的方法。 该方法包括实现多个可互操作的住宿和可访问性工具，并且提供与在界面上提供的多个可互操作的住宿和可访问性工具的测试接口。 该方法还包括接收用于指定多个可互操作的住宿和可访问性工具中的一个或多个允许的工具的测试者的一个或多个工具设置，以及基于一个或多个工具设置定制接口以允许测试者访问 在测试期间一个或多个允许的工具。 该方法还包括允许测试者激活或去激活一个或多个允许的工具中的每一个。

公开(公告)号：US20110006344A1

公开(公告)日：2011-01-13

申请号：US12655323

申请日：2009-12-29

申请人： Anand Murthy ,  Boyan Boyanov ,  Glenn A. Glass ,  Thomas Hoffmann

发明人： Anand Murthy ,  Boyan Boyanov ,  Glenn A. Glass ,  Thomas Hoffmann

IPC分类号： H01L29/06 ,  H01L21/336

CPC分类号： H01L29/7848 ,  H01L21/28518 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/36 ,  H01L29/41725 ,  H01L29/6628 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7833 ,  H01L29/7842 ,  Y10S438/933

摘要： An embodiment of the invention reduces the external resistance of a transistor by utilizing a silicon germanium alloy for the source and drain regions and a nickel silicon germanium self-aligned silicide (i.e., salicide) layer to form the contact surface of the source and drain regions. The interface of the silicon germanium and the nickel silicon germanium silicide has a lower specific contact resistivity based on a decreased metal-semiconductor work function between the silicon germanium and the silicide and the increased carrier mobility in silicon germanium versus silicon. The silicon germanium may be doped to further tune its electrical properties. A reduction of the external resistance of a transistor equates to increased transistor performance both in switching speed and power consumption.

公开(公告)号：US07851326B2

公开(公告)日：2010-12-14

申请号：US11812386

申请日：2007-06-18

申请人： Franz Dietz ,  Volker Dudek ,  Michael Graf ,  Thomas Hoffmann

发明人： Franz Dietz ,  Volker Dudek ,  Michael Graf ,  Thomas Hoffmann

IPC分类号： H01L21/76

CPC分类号： H01L21/76224

摘要： A method for producing deep trench structures in an STI structure of a semiconductor substrate is provided, with the following successive process steps: subsequent to a full-area filling of STI recesses introduced into a semiconductor substrate with a first filler material, a first surface of a semiconductor structure is subjected to a CMP process to level the applied filler material and produce the STI structure; the leveled STI structure thus produced is structured; using the structured, leveled STI structure as a hard mask, at least one deep trench is etched in the area of this STI structure to create the deep trench structures.

摘要翻译： 提供一种用于在半导体衬底的STI结构中制造深沟槽结构的方法，具有以下连续的工艺步骤：在用第一填充材料引入到半导体衬底中的STI凹部的全面填充之后， 对半导体结构进行CMP处理以对施加的填充材料进行平整并产生STI结构; 这样生产的水平STI结构是结构化的; 使用结构化的水平STI结构作为硬掩模，在该STI结构的区域中蚀刻至少一个深沟槽以产生深沟槽结构。

公开(公告)号：US20090057911A1

公开(公告)日：2009-03-05

申请号：US12203124

申请日：2008-09-02

申请人： Thomas Hoffmann ,  Stefan Schwantes

发明人： Thomas Hoffmann ,  Stefan Schwantes

IPC分类号： H01L21/768 ,  H01L23/522

CPC分类号： H01L21/743 ,  H01L21/76283 ,  H01L21/84

摘要： A method for manufacturing a semiconductor arrangement, use of a trench structure, and a semiconductor arrangement is provided that includes a single-crystal semiconductor layer, a conductive substrate region and a buried insulator layer, which isolates the single-crystal semiconductor layer from the conductive substrate region, whereby the conductive substrate region is contacted. A trench structure is formed to separate the single-crystal semiconductor layer into a first semiconductor region outside the trench structure and a second semiconductor region within the trench structure, an opening is formed in the single-crystal semiconductor layer within the second semiconductor region, the buried insulator layer is removed within the opening, and a conductor, which contacts the conductive substrate region and adjoins the second semiconductor region, is introduced into the opening.

摘要翻译： 提供一种制造半导体装置的方法，使用沟槽结构和半导体装置，其包括单晶半导体层，导电衬底区域和掩埋绝缘体层，其将单晶半导体层与导电 衬底区域，由此使导电衬底区域接触。 形成沟槽结构以将单晶半导体层分离成沟槽结构之外的第一半导体区域和沟槽结构内的第二半导体区域，在第二半导体区域内的单晶半导体层中形成开口， 在开口内去除埋入的绝缘体层，并且将与导电衬底区域接触并与第二半导体区域相邻接的导体引入到开口中。

公开(公告)号：US20080290856A1

公开(公告)日：2008-11-27

申请号：US12158785

申请日：2006-12-13

申请人： Thomas Hoffmann ,  Armin Liero

发明人： Thomas Hoffmann ,  Armin Liero

IPC分类号： G08C17/00

CPC分类号： G01R15/26 ,  G01R1/06777 ,  G01R1/06788

摘要： The invention relates to a device, a probe, and a method for the galvanically decoupling transmission of a measuring signal. A microwave signal is supplied by a transceiver (1) to a sensor (3) by means of a galvanically decoupled waveguide (2). The signal is partially reflected in the sensor (3), the amplitude, phase and/or polarization of the reflected microwave signal containing the information relating to the measuring value. The reflected microwave signal runs through the same waveguide (2) back to the transceiver (1) and is evaluated therein. The invention provides a more simple and economical structure than conventional devices of prior art, as a voltage supply is not required especially on the sensor side as a result of the reflection. In this way, the sensor (3) can also be produced in a very compact manner, minimizing the influence of the measuring signal through the sensor (3).

摘要翻译： 本发明涉及一种用于测量信号的电流去耦传输的装置，探针和方法。 微波信号由收发器（1）通过电流去耦波导（2）提供给传感器（3）。 信号部分地反映在传感器（3）中，反射的微波信号的振幅，相位和/或极化包含与测量值有关的信息。 反射的微波信号通过相同的波导（2）返回到收发器（1）并在其中进行评估。 本发明提供比现有技术的传统装置更简单和经济的结构，因为作为反射的结果，特别是传感器侧不需要电压源。 以这种方式，也可以以非常紧凑的方式制造传感器（3），从而最小化通过传感器（3）的测量信号的影响。

公开(公告)号：US20080290425A1

公开(公告)日：2008-11-27

申请号：US12119972

申请日：2008-05-13

申请人： Luis-Felipe Giles ,  Thomas Hoffmann ,  Chris Stapelmann

发明人： Luis-Felipe Giles ,  Thomas Hoffmann ,  Chris Stapelmann

IPC分类号： H01L29/00 ,  H01L21/425 ,  H01L21/336

CPC分类号： H01L21/3223 ,  H01L21/263 ,  H01L21/26506 ,  H01L29/66575 ,  H01L29/78

摘要： In a method for fabricating a semiconductor element in a substrate, first implantation ions are implanted into the substrate, whereby micro-cavities are produced in a first partial region of the substrate. Furthermore, pre-amorphization ions are implanted into the substrate, whereby a second partial region of the substrate is at least partly amorphized, and whereby crystal defects are produced in the substrate. Furthermore, second implantation ions are implanted into the second partial region of the substrate. Furthermore, the substrate is heated, such that at least some of the crystal defects are eliminated using the second implantation ions. Furthermore, dopant atoms are implanted into the second partial region of the substrate, wherein the semiconductor element is formed using the dopant atoms.

摘要翻译： 在衬底中制造半导体元件的方法中，将第一注入离子注入到衬底中，从而在衬底的第一部分区域中产生微腔。 此外，将非晶化离子注入到基板中，由此基板的第二部分区域至少部分非晶化，并且由此在基板中产生晶体缺陷。 此外，第二注入离子注入基片的第二部分区域。 此外，加热衬底，使得使用第二注入离子去除至少一些晶体缺陷。 此外，掺杂剂原子被注入到衬底的第二部分区域中，其中使用掺杂剂原子形成半导体元件。

公开(公告)号：US20070282705A1

公开(公告)日：2007-12-06

申请号：US11828864

申请日：2007-07-26

申请人： Geoff Chalmers ,  Thomas Hoffmann

发明人： Geoff Chalmers ,  Thomas Hoffmann

IPC分类号： G06Q30/00

CPC分类号： G06Q10/0837 ,  G06Q10/08 ,  G06Q10/087 ,  G06Q30/02 ,  G06Q30/0601 ,  G06Q40/04

摘要： The present invention provides systems and methods for processing return transactions over a network. An embodiment of the invention discloses an online return application that generates an electronic return shipping label that can be delivered to a browser of a customer that wishes to make a return. Also, disclosed is the creation and transmission of label delivery links, which provide for dynamic generation and delivery of shipping labels.

摘要翻译： 本发明提供了通过网络处理返回事务的系统和方法。 本发明的实施例公开了一种在线返回应用程序，其生成可以被递送到希望返回的客户的浏览器的电子退货运输标签。 此外，披露的是标签传送链接的创建和传输，其提供运输标签的动态生成和传递。

公开(公告)号：US07274055B2

公开(公告)日：2007-09-25

申请号：US11171097

申请日：2005-06-29

申请人： Anand Murthy ,  Boyan Boyanov ,  Glenn A. Glass ,  Thomas Hoffmann

发明人： Anand Murthy ,  Boyan Boyanov ,  Glenn A. Glass ,  Thomas Hoffmann

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/7848 ,  H01L21/28518 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/36 ,  H01L29/41725 ,  H01L29/6628 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7833 ,  H01L29/7842 ,  Y10S438/933

摘要： An embodiment of the invention reduces the external resistance of a transistor by utilizing a silicon germanium alloy for the source and drain regions and a nickel silicon germanium self-aligned silicide (i.e., salicide) layer to form the contact surface of the source and drain regions. The interface of the silicon germanium and the nickel silicon germanium silicide has a lower specific contact resistivity based on a decreased metal-semiconductor work function between the silicon germanium and the silicide and the increased carrier mobility in silicon germanium versus silicon. The silicon germanium may be doped to further tune its electrical properties. A reduction of the external resistance of a transistor equates to increased transistor performance both in switching speed and power consumption.

摘要翻译： 本发明的一个实施例通过利用用于源极和漏极区域的硅锗合金和镍硅锗自对准硅化物（即，自对准硅化物）层来形成源极和漏极区域的接触表面来降低晶体管的外部电阻 。 基于硅锗和硅化物之间的金属半导体功函数降低，硅锗与硅硅锗硅的界面具有较低的比接触电阻率，并且硅锗与硅中的载流子迁移率增加。 可以掺杂硅锗以进一步调整其电性能。 降低晶体管的外部电阻等同于在开关速度和功耗方面提高晶体管的性能。

公开(公告)号：US20060065937A1

公开(公告)日：2006-03-30

申请号：US10954914

申请日：2004-09-30

申请人： Thomas Hoffmann ,  Sunit Tyagi ,  Giuseppe Curello ,  Berhard Sell ,  Christopher Auth

发明人： Thomas Hoffmann ,  Sunit Tyagi ,  Giuseppe Curello ,  Berhard Sell ,  Christopher Auth

IPC分类号： H01L29/76 ,  H01L21/336

CPC分类号： H01L29/66636 ,  H01L21/26586 ,  H01L29/1083 ,  H01L29/41783 ,  H01L29/66492 ,  H01L29/7834 ,  H01L29/7848

摘要： A method of providing a halo implant region in a substrate of a MOS device having a gate electrode thereon and defining source/drain regions, a MOS device fabricated according to the above method, and a system comprising the MOS device. The method comprises: defining undercut recesses in the substrate at the source/drain regions thereof, the undercut recesses extending beneath the gate electrode; creating a halo implant region beneath the gate electrode between the recesses; and providing raised source/drain structures in the undercut recesses after creating the halo implant region.

摘要翻译： 在其上具有栅电极并限定源/漏区的MOS器件的衬底中提供卤素注入区的方法，根据上述方法制造的MOS器件和包括MOS器件的系统。 该方法包括：在其源极/漏极区域处限定衬底中的底切凹部，在栅电极下方延伸的底切凹部; 在所述凹部之间的所述栅极电极下面形成晕圈植入区域; 并且在产生晕圈植入区域之后在底切凹槽中提供升高的源极/漏极结构。