公开(公告)号：US4974241A

公开(公告)日：1990-11-27

申请号：US332290

申请日：1989-03-31

申请人： David C. McClure ,  Mark A. Lysinger

发明人： David C. McClure ,  Mark A. Lysinger

IPC分类号： G06F1/12 ,  G06F5/12 ,  G11C7/00 ,  H04J3/06 ,  H04L7/00

CPC分类号： H04J3/0626

摘要： The synchronization circuit of the preferred embodiment is a T flip flop which has a first output which changes state on the leading edge of the clock signal, and a second output which changes state on the trailing edge of the clock signal. The T flip flop has an exclusive OR gate input in which the T input is combined with the first output. The output of the exclusive OR is coupled to an internal node when the clock signal is at a first logic state, and isolated from the internal node when the clock signal is at a second logic state. The internal node is coupled to the first output when the clock signal is at the second logic sate and isolated from the internal node when the clock signal is at the first logic state. The first output signal is coupled to the second output signal when the clock signal is at the first logic state, and isolated from the second output terminal when the clock signal is at the second logic state.

公开(公告)号：US07978095B2

公开(公告)日：2011-07-12

申请号：US11473451

申请日：2006-06-23

申请人： David C. McClure ,  Sooping Saw ,  Robert Wadsworth

发明人： David C. McClure ,  Sooping Saw ,  Robert Wadsworth

IPC分类号： G08B13/14

CPC分类号： G11C16/20 ,  G11C16/22 ,  G11C17/16

摘要： An integrated circuit includes an output pad, an alarm output pad, and a test mode output pad. A first multi-bit register is programmable to store programmable data such as data that identifies a customer for whom the integrated circuit has been manufactured. A second multi-bit register is programmable to store customer specified threshold data. A first circuit selectively couples the first and second multi-bit registers to the output pad. The first circuit is operable responsive to the integrated circuit being placed into a test mode to perform parallel-to-serial conversion of either the customer identification data stored in the first multi-bit register or the customer specified threshold data stored in the second multi-bit register and drive the converted data for output through the output pad. The integrated circuit further includes a tamper detection circuit operable responsive to the customer specified threshold data to generate a tamper alarm signal. A second circuit selectively couples the tamper alarm signal to the alarm output pad and test mode output pad depending on whether the integrated circuit is in a test mode. More specifically, the second circuit operates to drive the alarm output pad with the tamper alarm signal when the integrated circuit is not in test mode and drive the test mode output pad with the tamper alarm signal when the integrated circuit is in test mode (with the alarm output pad driven to a known state).

摘要翻译： 集成电路包括输出焊盘，报警输出焊盘和测试模式输出焊盘。 第一个多位寄存器是可编程的，用于存储可编程数据，例如识别已经制造了集成电路的客户的数据。 可编程第二个多位寄存器来存储客户指定的阈值数据。 第一电路将第一和第二多位寄存器选择性地耦合到输出焊盘。 第一电路可操作地响应于集成电路被放置在测试模式中，以执行存储在第一多位寄存器中的客户识别数据或存储在第二多位寄存器中的客户指定的阈值数据的并行 - 串行转换， 位寄存器，并通过输出板驱动转换后的数据输出。 集成电路还包括可响应于客户指定的阈值数据操作的篡改检测电路，以产生篡改报警信号。 第二电路根据集成电路是否处于测试模式，选择性地将篡改报警信号耦合到报警输出焊盘和测试模式输出焊盘。 更具体地，当集成电路不处于测试模式时，第二电路用于驱动具有篡改报警信号的报警输出板，并且当集成电路处于测试模式时驱动具有篡改报警信号的测试模式输出板 报警输出板驱动到已知状态）。

公开(公告)号：US07724172B2

公开(公告)日：2010-05-25

申请号：US12020861

申请日：2008-01-28

申请人： David C. McClure ,  Sooping Saw

发明人： David C. McClure ,  Sooping Saw

IPC分类号： H03M1/78

CPC分类号： G01K3/005 ,  G01K7/015

摘要： A digital-to-analog converter, in response to a digital signal, selectively taps a resistor string to generate an analog output and selectively shunts around resistors in the string to voltage shift the analog output. If two supply voltage sets are present, two strings are provided. A mutually exclusively selection of outputs is made to select a source of the analog output. An integrated circuit temperature sensor uses the converter and includes a sensing circuit that determines exposure to one of a relatively low or high temperature. A measured voltage across the base-emitter of a bipolar transistor is selected in low temperature exposure and compared against a first reference for a too cold temperature condition. Alternatively, a measured delta voltage across the base-emitter is selected in high temperature exposure and compared against a second reference voltage for a too hot temperature condition. Through the comparisons, a temperature exposure detection is made.

摘要翻译： 数模转换器响应于数字信号，选择性地抽头电阻串以产生模拟输出，并选择性地分流串中的电阻器以对模拟输出进行电压移位。 如果存在两个电源电压组，则提供两个串。 选择输出的相互选择来选择模拟输出的源。 集成电路温度传感器使用转换器并且包括感测电路，其确定暴露于相对低或高温度之一。 在低温暴露下选择双极晶体管的基极 - 发射极两端的测量电压，并与太冷的温度条件下的第一参考值相比较。 或者，在高温暴露中选择基极 - 发射极两端的测量的增量电压，并与过热温度条件下的第二参考电压进行比较。 通过比较，进行温度曝光检测。

公开(公告)号：US20080198678A1

公开(公告)日：2008-08-21

申请号：US12029366

申请日：2008-02-11

申请人： David C. McClure ,  Mark A. Lysinger ,  Mehdi Zamanian ,  Francois Jacquet ,  Philippe Roche

发明人： David C. McClure ,  Mark A. Lysinger ,  Mehdi Zamanian ,  Francois Jacquet ,  Philippe Roche

IPC分类号： G11C5/14

CPC分类号： G11C11/417 ,  G11C5/147 ,  G11C5/148 ,  G11C11/41 ,  G11C11/413 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028

摘要： A memory circuit has a high voltage and low voltage supply nodes. One of a first and second sets of voltages is selectively applied to the supply nodes of the memory circuit in dependence upon memory operational mode. If in active read/write mode, then the first set of voltages is selectively applied. Conversely, if in standby no-read/no-write mode, then the second set of voltages is selectively applied. A low voltage in the second set of voltages is greater than a low voltage in the first set of voltages by a selected one of a plurality of low offset voltages, and a high voltage in the second set of voltages is less than a high voltage in the first set of voltages by a selected one of a plurality of high offset voltages. The offset voltages are provided by diode-based circuits that are selectively active. Selective activation is provided by either selectably blowable fuse elements or selectively activated switching elements.

摘要翻译： 存储电路具有高电压和低电压电源节点。 根据存储器操作模式，第一和第二组电压中的一个选择性地施加到存储器电路的供电节点。 如果处于主动读/写模式，则选择性地施加第一组电压。 相反，如果在备用无读/无写模式下，则选择性地施加第二组电压。 所述第二组电压中的低电压大于所述第一组电压中的低电压，所述第一组电压中的低电压通过多个低失调电压中的所选择的一个，并且所述第二组电压中的高电压小于所述第二组电压中的高电压 所述第一组电压通过多个高偏移电压中的所选择的一个。 偏移电压由选择性有效的基于二极管的电路提供。 选择性激活由可选择地可熔断的熔丝元件或选择性激活的开关元件提供。

公开(公告)号：US07362248B2

公开(公告)日：2008-04-22

申请号：US11474669

申请日：2006-06-26

申请人： David C. McClure ,  Sooping Saw

发明人： David C. McClure ,  Sooping Saw

IPC分类号： H03M1/00

CPC分类号： G01K3/005 ,  G01K7/015

摘要： A sensing circuit determines whether an integrated circuit is currently exposed to one of a relatively low or a relatively high temperature. A selection circuit selects a measured voltage across the base-emitter of a bipolar transistor if the sensing circuit indicates that the circuit is exposed to the relatively low temperature or, alternatively, selects a measured delta voltage across the base-emitter of the bipolar transistor if the sensing circuit indicates that the circuit is exposed to the relatively high temperature. A comparator compares the selected measured voltage against a first reference voltage indicative of a too cold temperature condition or compares the selected measured delta voltage against a second reference voltage indicative of a too hot temperature condition. As a result of the comparison, detection may be made as to whether the integrated circuit is currently exposed to a too cold or too hot temperature.

摘要翻译： 感测电路确定集成电路当前是否暴露于相对较低或相对高的温度之一。 如果感测电路指示电路暴露于相对较低的温度，则选择电路选择双极晶体管的基极 - 发射极两端的测量电压，或者，选择双极晶体管的基极 - 发射极两端的测量的增量电压，如果 感测电路指示电路暴露于相对较高的温度。 比较器将所选择的测量电压与指示太冷的温度条件的第一参考电压进行比较，或将所选择的测得的增量电压与指示过热温度条件的第二参考电压进行比较。 作为比较的结果，可以检测集成电路当前是否暴露于过冷或过热的温度。

公开(公告)号：US06754094B2

公开(公告)日：2004-06-22

申请号：US10066182

申请日：2002-01-31

申请人： David C. McClure

发明人： David C. McClure

IPC分类号： G11C1122

CPC分类号： G11C29/50 ,  G11C11/22 ,  G11C2029/5006

摘要： A test circuit and method are disclosed for testing memory cells of a ferroelectric memory device having an array of ferroelectric memory cells. The test circuitry is coupled to the bit lines, for selectively determining the voltage levels appearing on the bit lines based on a measured current level and providing externally to the ferroelectric memory device an electrical signal representative of the sensed voltage levels. In this way, ferroelectric memory cells exhibiting degraded performance may be identified.

摘要翻译： 公开了一种用于测试具有铁电存储器单元阵列的铁电存储器件的存储单元的测试电路和方法。 测试电路耦合到位线，用于基于测量的电流水平选择性地确定出现在位线上的电压电平，并在外部向铁电存储器件提供表示感测电压电平的电信号。 以这种方式，可以确定表现出降低性能的铁电存储器单元。

公开(公告)号：US06594192B1

公开(公告)日：2003-07-15

申请号：US09653495

申请日：2000-08-31

申请人： David C. McClure

发明人： David C. McClure

IPC分类号： G11C700

CPC分类号： G11C29/027 ,  G11C11/22 ,  G11C11/41 ,  G11C14/00 ,  G11C29/50 ,  G11C2029/5004

摘要： A memory device having a first and a second memory section, the first and the second memory sections being coupled to bit lines. The second memory section may include at least one fuse. The first memory section includes a volatile memory and the second memory section includes a non-volatile memory. The volatile memory may be static or dynamic random access memory. The memory device may further include a control circuit connected to the at least one fuse to provide for prelaser testing.

摘要翻译： 一种具有第一和第二存储器部分的存储器件，所述第一和第二存储器部分耦合到位线。 第二存储器部分可以包括至少一个熔丝。 第一存储器部分包括易失性存储器，并且第二存储器部分包括非易失性存储器。 易失性存储器可以是静态或动态随机存取存储器。 存储器件还可以包括连接到至少一个保险丝以提供预激光器测试的控制电路。

公开(公告)号：US5848018A

公开(公告)日：1998-12-08

申请号：US926833

申请日：1997-09-10

申请人： David C. McClure

发明人： David C. McClure

IPC分类号： G11C8/12 ,  G11C29/34 ,  G11C7/00

CPC分类号： G11C29/34 ,  G11C8/12

摘要： A memory-row selector includes an address input terminal, a mode terminal, and even-row-select and odd-row-select terminals. While a test signal level occupies the mode terminal (ie., during a test mode), the selector places either an active level or an inactive level on both of the even-row-select and odd-row-select terminals. An active level on both of the select terminals enables both even-row and odd-row word lines, and allows writing to or reading from memory cells in both odd and even rows. An inactive level on both of the select terminals disables both even-row and odd-row word lines, including the word line coupled to the addressed memory cell.

摘要翻译： 存储行选择器包括地址输入端子，模式端子，偶数行选择和奇数行选择端子。 当测试信号电平占用模式终端（即，在测试模式期间）时，选择器将两个偶数行选择端子和奇数行选择端子置为有效电平或无效电平。 两个选择端子上的有效电平使能偶数行和奇数行字线，并允许写入或读取奇数行和偶数行中的存储单元。 两个选择端子上的无效电平禁止偶数行和奇数行字线，包括耦合到寻址存储单元的字线。

公开(公告)号：US5808960A

公开(公告)日：1998-09-15

申请号：US858295

申请日：1997-05-19

申请人： David C. McClure

发明人： David C. McClure

IPC分类号： G11C11/413 ,  G11C7/10 ,  G11C7/22 ,  G11C29/02 ,  G11C29/50 ,  G11C8/00

CPC分类号： G11C29/025 ,  G11C29/02 ,  G11C29/50 ,  G11C29/50012 ,  G11C7/1078 ,  G11C7/22 ,  G11C11/41

摘要： A circuit and method for determining the exact time at which data begins to be written to a memory cell. A write sensing circuit is connected to a data input line. When data is presented on the data input line for writing to the memory cell, the write sensing circuit outputs a write start signal indicating that data is being presented to memory cells for writing. The actual start time of a write to a memory cell is therefore accurately timed based on the start of the write to the memory cell itself. This provides the advantage that the change in state of the data is directly sensed as the factor for measuring the start time of a write to a memory cell. The data can be sensed either directly from the bit lines or, alternatively, from a write data bus.

摘要翻译： 用于确定数据开始被写入存储单元的确切时间的电路和方法。 写入感测电路连接到数据输入线。 当在用于写入存储器单元的数据输入线上呈现数据时，写入感测电路将表示正在呈现数据的写入开始信号输出到用于写入的存储单元。 因此，写入存储器单元的实际开始时间基于对存储器单元本身的写入的开始精确地定时。 这提供了以下优点：数据的状态变化被直接感测为用于测量写入存储器单元的开始时间的因素。 可以直接从位线或者写入数据总线来感测数据。

公开(公告)号：US5808947A

公开(公告)日：1998-09-15

申请号：US710357

申请日：1996-09-17

申请人： David C. McClure

发明人： David C. McClure

IPC分类号： G01R31/28 ,  G01R31/30 ,  G01R31/3185 ,  G06F11/22 ,  G11C29/00 ,  G11C29/26 ,  G11C29/56 ,  H01L23/58 ,  G11C13/00

CPC分类号： G01R31/30 ,  G01R31/318505 ,  G01R31/318511 ,  G11C29/26 ,  H01L22/32 ,  G06F11/2273 ,  H01L2924/0002 ,  H01L2924/3011

摘要： An integrated circuit is formed on a die that is formed as a detachable part of a semiconductor wafer. The wafer includes both a wafer test-mode path that is operable to carry a wafer test-mode signal and a wafer power-supply path that is operable to carry a wafer power-supply signal. The integrated circuit includes functional circuitry that supports normal and wafer-test modes of operation and that is coupled to the wafer test-mode path before the die is detached from the wafer. The functional circuitry is operable to function in the wafer test mode of operation when the wafer test-mode signal has a first state. The integrated circuit also includes a wafer test-mode power circuit that is coupled to the functional circuitry, and that is coupled to the wafer power-supply path and the wafer test-mode path before the die is detached from the wafer. The power circuit is operable to couple the wafer power-supply path to the functional circuitry when the wafer test-mode signal has the first state. When the wafer test-mode signal has a second state, the wafer test-mode power circuit is operable to uncouple the wafer power-supply path from the functional circuitry, and the functional circuitry is operable to function in the normal mode of operation.

摘要翻译： 集成电路形成在作为半导体晶片的可拆卸部分形成的裸片上。 晶片包括可操作以承载晶片测试模式信号的晶片测试模式路径和可操作以承载晶片电源信号的晶片供电路径。 集成电路包括支持正常和晶片测试操作模式的功能电路，并且在芯片与晶片分离之前耦合到晶片测试模式路径。 当晶片测试模式信号具有第一状态时，功能电路可操作以在晶片测试操作模式中起作用。 集成电路还包括耦合到功能电路的晶片测试模式电源电路，并且在芯片从晶片分离之前耦合到晶片供电路径和晶片测试模式路径。 当晶片测试模式信号具有第一状态时，电源电路可操作以将晶片供电路径耦合到功能电路。 当晶片测试模式信号具有第二状态时，晶片测试模式电源电路可操作用于将晶片供电路径从功能电路断开，并且功能电路可操作以在正常工作模式下工作。