公开(公告)号：US20080198678A1

公开(公告)日：2008-08-21

申请号：US12029366

申请日：2008-02-11

申请人： David C. McClure ,  Mark A. Lysinger ,  Mehdi Zamanian ,  Francois Jacquet ,  Philippe Roche

发明人： David C. McClure ,  Mark A. Lysinger ,  Mehdi Zamanian ,  Francois Jacquet ,  Philippe Roche

IPC分类号： G11C5/14

CPC分类号： G11C11/417 ,  G11C5/147 ,  G11C5/148 ,  G11C11/41 ,  G11C11/413 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028

摘要： A memory circuit has a high voltage and low voltage supply nodes. One of a first and second sets of voltages is selectively applied to the supply nodes of the memory circuit in dependence upon memory operational mode. If in active read/write mode, then the first set of voltages is selectively applied. Conversely, if in standby no-read/no-write mode, then the second set of voltages is selectively applied. A low voltage in the second set of voltages is greater than a low voltage in the first set of voltages by a selected one of a plurality of low offset voltages, and a high voltage in the second set of voltages is less than a high voltage in the first set of voltages by a selected one of a plurality of high offset voltages. The offset voltages are provided by diode-based circuits that are selectively active. Selective activation is provided by either selectably blowable fuse elements or selectively activated switching elements.

摘要翻译： 存储电路具有高电压和低电压电源节点。 根据存储器操作模式，第一和第二组电压中的一个选择性地施加到存储器电路的供电节点。 如果处于主动读/写模式，则选择性地施加第一组电压。 相反，如果在备用无读/无写模式下，则选择性地施加第二组电压。 所述第二组电压中的低电压大于所述第一组电压中的低电压，所述第一组电压中的低电压通过多个低失调电压中的所选择的一个，并且所述第二组电压中的高电压小于所述第二组电压中的高电压 所述第一组电压通过多个高偏移电压中的所选择的一个。 偏移电压由选择性有效的基于二极管的电路提供。 选择性激活由可选择地可熔断的熔丝元件或选择性激活的开关元件提供。

公开(公告)号：US07688669B2

公开(公告)日：2010-03-30

申请号：US12029366

申请日：2008-02-11

申请人： David C. McClure ,  Mark A. Lysinger ,  Mehdi Zamanian ,  François Jacquet ,  Philippe Roche

发明人： David C. McClure ,  Mark A. Lysinger ,  Mehdi Zamanian ,  François Jacquet ,  Philippe Roche

IPC分类号： G11C7/00

CPC分类号： G11C11/417 ,  G11C5/147 ,  G11C5/148 ,  G11C11/41 ,  G11C11/413 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028

摘要： A memory circuit has a high voltage and low voltage supply nodes. One of a first and second sets of voltages is selectively applied to the supply nodes of the memory circuit in dependence upon memory operational mode. If in active read/write mode, then the first set of voltages is selectively applied. Conversely, if in standby no-read/no-write mode, then the second set of voltages is selectively applied. A low voltage in the second set of voltages is greater than a low voltage in the first set of voltages by a selected one of a plurality of low offset voltages, and a high voltage in the second set of voltages is less than a high voltage in the first set of voltages by a selected one of a plurality of high offset voltages. The offset voltages are provided by diode-based circuits that are selectively active. Selective activation is provided by either selectably blowable fuse elements or selectively activated switching elements.

摘要翻译： 存储电路具有高电压和低电压电源节点。 根据存储器操作模式，第一和第二组电压中的一个选择性地施加到存储器电路的供电节点。 如果处于主动读/写模式，则选择性地施加第一组电压。 相反，如果在备用无读/无写模式下，则选择性地施加第二组电压。 所述第二组电压中的低电压大于所述第一组电压中的低电压，所述第一组电压中的低电压通过多个低失调电压中的所选择的一个，并且所述第二组电压中的高电压小于所述第二组电压中的高电压 所述第一组电压通过多个高偏移电压中的所选择的一个。 偏移电压由选择性有效的基于二极管的电路提供。 选择性激活由可选择地可熔断的熔丝元件或选择性激活的开关元件提供。

公开(公告)号：US5544097A

公开(公告)日：1996-08-06

申请号：US414918

申请日：1995-03-31

申请人： David C. McClure ,  Mehdi Zamanian

发明人： David C. McClure ,  Mehdi Zamanian

IPC分类号： G11C11/413 ,  G11C5/14 ,  G11C11/412 ,  G11C11/40

CPC分类号： G11C5/147 ,  G11C11/412

摘要： A memory cell having a first device operable to selectively conduct and coupled between a first cell node and a low voltage reference node and a second device operable to selectively conduct and coupled between a second cell node and the low voltage reference node. The memory cell further includes a first and second data line and circuitry for receiving a system level voltage and for biasing the first and second data lines at a first and second data voltage, respectively. Still further, the memory cell includes circuitry for coupling the first and second data line to the first and second cell node, respectively, such that a logical high voltage is selectively written to one of the first and second cell nodes while a logical low is written to the other of the first and second cell nodes during a write operation. Still further, the memory cell includes a voltage source node for receiving a cell voltage and circuitry for coupling the voltage source node to the first and second cell nodes. Lastly, the memory cell includes cell voltage circuitry for generating the cell voltage, wherein the cell voltage circuitry is operable to output a cell voltage less than the system level voltage.

摘要翻译： 一种具有第一装置的存储器单元，其可操作以选择性地传导和耦合在第一单元节点和低电压参考节点之间，以及可操作以选择性地传导和耦合在第二单元节点与低电压参考节点之间的第二设备。 存储单元还包括第一和第二数据线以及用于接收系统电平电压并用于分别以第一和第二数据电压偏置第一和第二数据线的电路。 另外，存储单元包括用于将第一和第二数据线分别耦合到第一和第二单元节点的电路，使得逻辑高电压有选择地写入第一和第二单元节点中的一个，同时写入逻辑低电平 在写入操作期间到第一和第二小区节点中的另一个。 此外，存储单元包括用于接收单元电压的电压源节点和用于将电压源节点耦合到第一和第二单元节点的电路。 最后，存储单元包括用于产生单元电压的单元电压电路，其中单元电压电路可操作以输出小于系统电平电压的单元电压。

公开(公告)号：US07064534B2

公开(公告)日：2006-06-20

申请号：US10695294

申请日：2003-10-27

申请人： David C. McClure ,  Mehdi Zamanian

发明人： David C. McClure ,  Mehdi Zamanian

IPC分类号： G05F3/16

CPC分类号： G05F3/247 ,  Y10T307/615 ,  Y10T307/696

摘要： A regulator circuit and method are disclosed for a system. The regulator circuit may include a compare circuit for comparing a first supply voltage to a predetermined voltage level and generating an enable signal based upon the comparison. A selectively enabled voltage regulator is adapted to make available a predetermined current level at a regulated voltage when enabled by the compare circuit. When disabled, the voltage regulator circuit is prohibited from providing current. The voltage regulator may include an output transistor that is normally biased in a saturation mode of operation and is deactivated by the enable signal. By controlling the output transistor based upon the output of the compare circuit, the need for a relatively large transistor for connecting to the first supply voltage is eliminated.

摘要翻译： 公开了一种用于系统的调节器电路和方法。 调节器电路可以包括用于将第一电源电压与预定电压电平进行比较并基于该比较产生使能信号的比较电路。 当由比较电路使能时，有选择地使能的电压调节器适于使得在调节电压下可用的预定电流电平。 禁用时，电压调节器电路禁止提供电流。 电压调节器可以包括通常在饱和运行模式下被偏置并由使能信号禁用的输出晶体管。 通过基于比较电路的输出控制输出晶体管，消除了用于连接到第一电源电压的相对大的晶体管的需要。

公开(公告)号：US6033980A

公开(公告)日：2000-03-07

申请号：US978382

申请日：1997-11-25

申请人： Fu-Tai Liou ,  Mehdi Zamanian

发明人： Fu-Tai Liou ,  Mehdi Zamanian

IPC分类号： H01L21/302 ,  H01L21/3065 ,  H01L21/768 ,  H01L23/522 ,  H01L21/31

CPC分类号： H01L21/76831 ,  H01L21/76807

摘要： A method is provided of forming a small geometry via or contact of a semiconductor integrated circuit, and an integrated circuit formed according to the same, is disclosed. According to a first disclosed embodiment, an opening is formed partially through an insulating layer overlying a conductive region. Sidewall spacers are formed along the sidewalls of the opening. The remaining insulating layer is etched to expose the underlying conductive region. The contact dimension of the opening is smaller than the opening which can be printed from modern photolithography techniques. According to an alternate embodiment, the opening in the insulating layer expose the underlying conductive region. A polysilicon layer is formed over the insulating layer and in the opening. The polysilicon is oxidized to form a thick oxide in the opening and is etched back to form oxidized polysilicon sidewall spacers which decrease the contact dimension of the opening. According to a further alternate embodiment, an etch stop layer is formed between the insulating layer and conductive region and an opening is formed in the insulating layer exposing the etch stop layer. A sidewall spacer film is formed over the insulating layer and the etch stop layer, both layers having a similar etch rate for a given etchant. The etch stop and spacer layers are etched in the opening to expose the underlying conductive layer thereby forming a contiguous sidewall spacer and etch stop layer on the sides of and under the insulating layer, thereby decreasing the contact dimension of the opening.

公开(公告)号：US20060001039A1

公开(公告)日：2006-01-05

申请号：US10881701

申请日：2004-06-30

申请人： Mehdi Zamanian

发明人： Mehdi Zamanian

IPC分类号： H01L29/24 ,  H01L21/336 ,  H01L21/31

CPC分类号： B81B1/00 ,  B01J19/0093 ,  B01J2219/00783 ,  B01J2219/00819 ,  B01J2219/00873 ,  B01L3/502707 ,  B01L7/52 ,  B01L2200/12 ,  B01L2300/0816 ,  B01L2300/1827 ,  B81B2201/058

摘要： A method of manufacturing an integrated device that includes filling at least one channel region of a substrate with a sacrificial material to form a filled channel, forming an encapsulating layer over the filled channel, forming an aperture in the encapsulating layer, and selectively removing the sacrificial material in the channel region is described. The sacrificial material and etchant can be selected so that the sacrificial material is etched faster than the substrate and/or encapsulating layer. An integrated device having a substrate, at least one channel formed in the substrate, an encapsulating layer located over the substrate and over at least a portion of the channel, the encapsulating layer having at least one aperture located over the channel is also described.

摘要翻译： 一种制造集成器件的方法，其包括用牺牲材料填充衬底的至少一个沟道区域以形成填充沟道，在填充沟道上形成封装层，在封装层中形成孔，并选择性地去除牺牲层 描述了通道区域中的材料。 可以选择牺牲材料和蚀刻剂，使得牺牲材料比衬底和/或封装层更快地被蚀刻。 还描述了一种具有衬底的集成器件，在衬底中形成的至少一个沟道，位于衬底上方以及至少部分沟道上的封装层，封装层具有位于沟道上方的至少一个孔。

公开(公告)号：US20050088152A1

公开(公告)日：2005-04-28

申请号：US10695294

申请日：2003-10-27

申请人： David McClure ,  Mehdi Zamanian

发明人： David McClure ,  Mehdi Zamanian

IPC分类号： G05F1/40 ,  G05F3/24

CPC分类号： G05F3/247 ,  Y10T307/615 ,  Y10T307/696

摘要： A regulator circuit and method are disclosed for a system. The regulator circuit may include a compare circuit for comparing a first supply voltage to a predetermined voltage level and generating an enable signal based upon the comparison. A selectively enabled voltage regulator is adapted to make available a predetermined current level at a regulated voltage when enabled by the compare circuit. When disabled, the voltage regulator circuit is prohibited from providing current. The voltage regulator may include an output transistor that is normally biased in a saturation mode of operation and is deactivated by the enable signal. By controlling the output transistor based upon the output of the compare circuit, the need for a relatively large transistor for connecting to the first supply voltage is eliminated.

摘要翻译： 公开了一种用于系统的调节器电路和方法。 调节器电路可以包括用于将第一电源电压与预定电压电平进行比较并基于该比较产生使能信号的比较电路。 当由比较电路使能时，有选择地使能的电压调节器适于使得在调节电压下可用的预定电流电平。 禁用时，电压调节器电路禁止提供电流。 电压调节器可以包括通常在饱和运行模式下被偏置并由使能信号禁用的输出晶体管。 通过基于比较电路的输出控制输出晶体管，消除了用于连接到第一电源电压的相对大的晶体管的需要。

公开(公告)号：US06295224B1

公开(公告)日：2001-09-25

申请号：US09475101

申请日：1999-12-30

申请人： Tsiu Chiu Chan ,  Mehdi Zamanian ,  David Charles McClure

发明人： Tsiu Chiu Chan ,  Mehdi Zamanian ,  David Charles McClure

IPC分类号： G11C1100

CPC分类号： H01L27/11 ,  G11C11/412

摘要： A circuit and method is disclosed for a memory cell for a static random access memory. The memory cell includes a pair of cross-coupled CMOS logic inverters that are connected together to form a latch, and a pair of p-channel transmission gate transistors that are connected to the logic inverters for selectively providing access to the latch. The layout of the memory cell includes a rectangular active area in which the p-channel transistors of the memory cell are located. The rectangular active area abuts a similar active area of an adjacent memory cell along a row of memory cells so as to form a single rectangular active area for the p-channel memory cell transistors. The rectangular active area reduces the occurrence of fabrication-related phenomena that adversely effect the performance of the memory cell.

摘要翻译： 公开了一种用于静态随机存取存储器的存储单元的电路和方法。 存储单元包括连接在一起以形成锁存器的一对交叉耦合CMOS逻辑反相器，以及连接到逻辑反相器的一对p沟道传输栅极晶体管，用于选择性地提供对锁存器的访问。 存储单元的布局包括存储单元的p沟道晶体管位于其中的矩形有源区。 矩形有源区域沿着一行存储器单元邻接相邻存储器单元的类似有效区域，以形成用于p沟道存储单元晶体管的单个矩形有源区域。 矩形有源区减少了不利地影响存储单元的性能的制造相关现象的发生。

公开(公告)号：US06180517B2

公开(公告)日：2001-01-30

申请号：US08948904

申请日：1997-10-10

申请人： Fu-Tai Liou ,  Mehdi Zamanian

发明人： Fu-Tai Liou ,  Mehdi Zamanian

IPC分类号： H01L214763

CPC分类号： H01L21/76831 ,  H01L21/76802 ,  H01L21/76807

摘要： A method is provided of forming a small geometry via or contact of a semiconductor integrated circuit, and an integrated circuit formed according to the same, is disclosed. According to a first disclosed embodiment, an opening is formed partially through an insulating layer overlying a conductive region. Sidewall spacers are formed along the sidewalls of the opening. The remaining insulating layer is etched to expose the underlying conductive region. The contact dimension of the opening is smaller than the opening which can be printed from modern photolithography techniques. According to an alternate embodiment, the opening in the insulating layer expose the underlying conductive region. A polysilicon layer is formed over the insulating layer and in the opening. The polysilicon is oxidized to form a thick oxide in the opening and is etched back to form oxidized polysilicon sidewall spacers which decrease the contact dimension of the opening. According to a further alternate embodiment, an etch stop layer is formed between the insulating layer and conductive region and an opening is formed in the insulating layer exposing the etch stop layer. A sidewall spacer film is formed over the insulating layer and the etch stop layer, both layers having a similar etch rate for a given etchant. The etch stop and spacer layers are etched in the opening to expose the underlying conductive layer thereby forming a contiguous sidewall spacer and etch stop layer on the sides of and under the insulating layer, thereby decreasing the contact dimension of the opening.

摘要翻译： 公开了一种通过半导体集成电路或接触形成小几何形状的方法，以及根据该半导体集成电路形成的集成电路。 根据第一公开的实施例，部分地通过覆盖导电区域的绝缘层形成开口。 沿着开口的侧壁形成侧壁间隔物。 蚀刻剩余的绝缘层以暴露下面的导电区域。 开口的接触尺寸小于可以用现代光刻技术印刷的开口。 根据替代实施例，绝缘层中的开口暴露下面的导电区域。 在绝缘层和开口中形成多晶硅层。 多晶硅被氧化以在开口中形成厚的氧化物并被回蚀以形成减小开口的接触尺寸的氧化的多晶硅侧壁间隔物。 根据另一替代实施例，在绝缘层和导电区域之间形成蚀刻停止层，并且在暴露蚀刻停止层的绝缘层中形成开口。 在绝缘层和蚀刻停止层上形成侧壁间隔膜，两层对于给定的蚀刻剂具有相似的蚀刻速率。 蚀刻停止层和间隔层在开口中被蚀刻以暴露下面的导电层，从而在绝缘层上和下方形成连续的侧壁间隔物和蚀刻停止层，从而减小开口的接触尺寸。

公开(公告)号：US6091630A

公开(公告)日：2000-07-18

申请号：US393125

申请日：1999-09-10

申请人： Tsiu C. Chan ,  Mehdi Zamanian

发明人： Tsiu C. Chan ,  Mehdi Zamanian

IPC分类号： H01L21/8244 ,  H01L27/11 ,  G11C11/00

CPC分类号： H01L27/1104

摘要： A radiation hardened memory device having static random access memory cells includes active gate isolation structures placed in series with oxide isolation regions between the active regions of a memory cell array. The active gate isolation structure includes a gate oxide and polycrystalline silicon gate layer electrically coupled to a supply terminal resulting in an active gate isolation structure that prevents a conductive channel extending from adjacent active regions from forming. The gate oxide of the active gate isolation structures is relatively thin compared to the conventional oxide isolation regions and thus, will be less susceptible to any adverse influence from trapped charges caused by radiation exposure.

摘要翻译： 具有静态随机存取存储器单元的辐射硬化存储器件包括与存储器单元阵列的有源区之间的氧化物隔离区域串联设置的有源栅极隔离结构。 有源栅极隔离结构包括电耦合到电源端的栅极氧化物和多晶硅栅极层，导致有源栅极隔离结构，其防止从相邻的有源区域延伸的导电沟道形成。 与常规的氧化物隔离区域相比，有源栅极隔离结构的栅极氧化物相对较薄，因此不太容易受到由辐射暴露引起的俘获电荷的任何不利影响。