公开(公告)号：US08766430B2

公开(公告)日：2014-07-01

申请号：US13517654

申请日：2012-06-14

Applicant: Ralf Otremba ,  Davide Chiola ,  Erich Griebl ,  Fabio Brucchi

Inventor： Ralf Otremba ,  Davide Chiola ,  Erich Griebl ,  Fabio Brucchi

IPC: H01L23/48

CPC classification number: H01L23/49562 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/36 ,  H01L23/4952 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L25/11 ,  H01L2224/04042 ,  H01L2224/0603 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48464 ,  H01L2224/4903 ,  H01L2924/00014 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/181 ,  H05K1/0296 ,  H05K3/308 ,  H05K2201/0792 ,  H05K2201/10166 ,  H05K2201/10522 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/00012

Abstract: In accordance with an embodiment of the present invention, a semiconductor module includes a first semiconductor device having a first plurality of leads including a first gate/base lead, a first drain/collector lead, and a first source/emitter lead. The module further includes a second semiconductor device and a circuit board. The second semiconductor device has a second plurality of leads including a second gate/base lead, a second drain/collector lead, and a second source/emitter lead. The circuit board has a plurality of mounting holes, wherein each of the first plurality of leads and the second plurality of leads is mounted into a respective one of the plurality of mounting holes. At the plurality of mounting holes, a first distance from the first gate/base lead to the second gate/base lead is different from a second distance from the first source/emitter lead to the second source/emitter lead.

Abstract translation: 根据本发明的实施例，半导体模块包括具有包括第一栅极/基极引线，第一漏极/集电极引线和第一源极/发射极引线的第一多个引线的第一半导体器件。 该模块还包括第二半导体器件和电路板。 第二半导体器件具有包括第二栅极/基极引线，第二漏极/集电极引线和第二源极/发射极引线的第二多个引线。 电路板具有多个安装孔，其中第一多个引线和第二多个引线中的每一个安装到多个安装孔中的相应一个安装孔中。 在多个安装孔处，从第一栅极/基极引线到第二栅极/基极引线的第一距离与从第一源极/发射极引线到第二源极/发射极引线的第二距离不同。

公开(公告)号：US08304305B2

公开(公告)日：2012-11-06

申请号：US13156037

申请日：2011-06-08

Applicant: Davide Chiola ,  Carsten Schaeffer

Inventor： Davide Chiola ,  Carsten Schaeffer

IPC: H01L21/8238

CPC classification number: H01L29/7397 ,  H01L29/0623 ,  H01L29/0834 ,  H01L29/66348

Abstract: A method for producing a semiconductor component is proposed. The method includes providing a semiconductor body having a first surface; forming a mask on the first surface, wherein the mask has openings for defining respective positions of trenches; producing the trenches in the semiconductor body using the mask, wherein mesa structures remain between adjacent trenches; introducing a first dopant of a first conduction type using the mask into the bottoms of the trenches; carrying out a first thermal step; introducing a second dopant of a second conduction type, which is complementary to the first conduction type, at least into the bottoms of the trenches; and carrying out a second thermal step.

Abstract translation: 提出了半导体元件的制造方法。 该方法包括提供具有第一表面的半导体本体; 在所述第一表面上形成掩模，其中所述掩模具有用于限定沟槽的相应位置的开口; 使用掩模在半导体本体中产生沟槽，其中台面结构保留在相邻的沟槽之间; 使用掩模将第一导电类型的第一掺杂剂引入沟槽的底部; 进行第一热步骤; 将与第一导电类型互补的第二导电类型的第二掺杂剂至少引入到沟槽的底部; 并进行第二热步骤。

公开(公告)号：US08143655B2

公开(公告)日：2012-03-27

申请号：US11974103

申请日：2007-10-11

Applicant: Davide Chiola

Inventor： Davide Chiola

IPC: H01L21/02

CPC classification number: H01L29/8725 ,  H01L27/0814 ,  H01L29/0661 ,  H01L29/407 ,  H01L29/66143 ,  H01L29/872 ,  Y10S438/963

Abstract: A fabrication process for a trench Schottky diode with differential oxide thickness within the trenches includes forming a first nitride layer on a substrate surface and subsequently forming a plurality of trenches in the substrate including, possibly, a termination trench. Following a sacrificial oxide layer formation and removal, sidewall and bottom surfaces of the trenches are oxidized. A second nitride layer is then applied to the substrate and etched such that the second nitride layer covers the oxide layer on the trench sidewalls but exposes the oxide layer on the trench bottom surfaces. The trench bottom surfaces are then re-oxidized and the remaining second nitride layer then removed from the sidewalls, resulting in an oxide layer of varying thickness being formed on the sidewall and bottom surfaces of each trench. The trenches are then filled with a P type polysilicon, the first nitride layer removed, and a Schottky barrier metal applied to the substrate surface.

Abstract translation: 在沟槽内具有差的氧化物厚度的沟槽肖特基二极管的制造方法包括在衬底表面上形成第一氮化物层，并且随后在衬底中形成多个沟槽，包括可能的端接沟槽。 在牺牲氧化层形成和去除之后，沟槽的侧壁和底表面被氧化。 然后将第二氮化物层施加到衬底并被蚀刻，使得第二氮化物层覆盖沟槽侧壁上的氧化物层，但是暴露出沟槽底表面上的氧化物层。 然后，沟槽底表面被再次氧化，然后从侧壁去除剩余的第二氮化物层，导致在每个沟槽的侧壁和底表面上形成不同厚度的氧化物层。 然后用P型多晶硅，去除第一氮化物层和施加到衬底表面上的肖特基势垒金属填充沟槽。

公开(公告)号：US06991943B2

公开(公告)日：2006-01-31

申请号：US10728482

申请日：2003-12-04

Applicant: Kohji Andoh ,  Davide Chiola

Inventor： Kohji Andoh ,  Davide Chiola

IPC: H01L21/00

CPC classification number: H01L22/20

Abstract: A method for adjusting the resistivity in the surface of a semiconductive substrate including selective measurement and counter-doping of areas on a major surface of a semiconductive substrate.

Abstract translation: 一种用于调整半导体衬底的表面中的电阻率的方法，包括半导体衬底的主表面上的区域的选择性测量和反掺杂。

公开(公告)号：US20050202637A1

公开(公告)日：2005-09-15

申请号：US11077929

申请日：2005-03-11

Applicant: Davide Chiola

Inventor： Davide Chiola

IPC: H01L21/336

CPC classification number: H01L29/8725 ,  H01L29/0619 ,  H01L29/66143

Abstract: A trench type Schottky device has a guard ring diffusion of constant depth between the outermost of an active trench and an outer surrounding termination trench. The junction curvature of the guard ring diffusion is suppressed or cut out by the trenches.

Abstract translation: 沟槽式肖特基器件具有在有源沟槽的最外部和外部周围终止沟槽之间的恒定深度的保护环扩散。 保护环扩散的接合曲率被沟槽抑制或切除。

公开(公告)号：US20050127465A1

公开(公告)日：2005-06-16

申请号：US11035582

申请日：2005-01-14

Applicant: Davide Chiola

Inventor： Davide Chiola

IPC: H01L21/329 ,  H01L27/08 ,  H01L29/40 ,  H01L29/47 ,  H01L29/872 ,  H01L29/76

CPC classification number: H01L29/8725 ,  H01L27/0814 ,  H01L29/0661 ,  H01L29/407 ,  H01L29/66143 ,  H01L29/872 ,  Y10S438/963

Abstract: A fabrication process for a trench Schottky diode with differential oxide thickness within the trenches includes forming a first nitride layer on a substrate surface and subsequently forming a plurality of trenches in the substrate including, possibly, a termination trench. Following a sacrificial oxide layer formation and removal, sidewall and bottom surfaces of the trenches are oxidized. A second nitride layer is then applied to the substrate and etched such that the second nitride layer covers the oxide layer on the trench sidewalls but exposes the oxide layer on the trench bottom surfaces. The trench bottom surfaces are then re-oxidized and the remaining second nitride layer then removed from the sidewalls, resulting in an oxide layer of varying thickness being formed on the sidewall and bottom surfaces of each trench. The trenches are then filled with a P type polysilicon, the first nitride layer removed, and a Schottky barrier metal applied to the substrate surface.

Abstract translation: 在沟槽内具有差的氧化物厚度的沟槽肖特基二极管的制造方法包括在衬底表面上形成第一氮化物层，并且随后在衬底中形成多个沟槽，包括可能的端接沟槽。 在牺牲氧化层形成和去除之后，沟槽的侧壁和底表面被氧化。 然后将第二氮化物层施加到衬底并被蚀刻，使得第二氮化物层覆盖沟槽侧壁上的氧化物层，但是暴露出沟槽底表面上的氧化物层。 然后，沟槽底表面被再次氧化，然后从侧壁去除剩余的第二氮化物层，导致在每个沟槽的侧壁和底表面上形成不同厚度的氧化物层。 然后用P型多晶硅，去除第一氮化物层和施加到衬底表面上的肖特基势垒金属填充沟槽。

公开(公告)号：US20050062124A1

公开(公告)日：2005-03-24

申请号：US10936162

申请日：2004-09-08

Applicant: Davide Chiola

Inventor： Davide Chiola

IPC: H01L29/06 ,  H01L29/40 ,  H01L29/872 ,  H01L29/76

CPC classification number: H01L29/8725 ,  H01L29/0661 ,  H01L29/407 ,  H01L29/66143 ,  H01L29/872

Abstract: A schottky diode of the trench variety which includes a trench termination having a thick insulation layer that is thicker than the insulation layer inside the trenches in its active region.

Abstract translation: 沟槽品种的肖特基二极管，其包括具有比其活性区域中的沟槽内的绝缘层厚的厚绝缘层的沟槽端子。