公开(公告)号：US20160110119A1

公开(公告)日：2016-04-21

申请号：US14515500

申请日：2014-10-15

申请人： Prabhjot Singh ,  Nitin Gera ,  Hemant Nautiyal

发明人： Prabhjot Singh ,  Nitin Gera ,  Hemant Nautiyal

IPC分类号： G06F3/06 ,  G06F13/16 ,  G06F13/28

CPC分类号： G06F3/0613 ,  G06F3/0659 ,  G06F3/0679 ,  G06F13/1694 ,  G06F13/28 ,  G06F2206/1014

摘要： In a processing system, an integrated function controller (IFC) for one or more memory devices, including a NAND flash memory device, provides direct memory access (DMA) functionality for writing data to and reading data from the NAND flash memory device, thereby reducing the level of CPU intervention required to support such operations. In one implementation, the CPU stores in system memory a descriptor-based DMA operation sequence of NAND flash operations and then triggers the IFC to implement the descriptor sequence. The IFC sequentially fetches and implements individual stored descriptors without interrupting the CPU or requiring any real-time CPU intervention using, for example, a “repeat while busy” polling descriptor type. The IFC frees up the CPU to perform other system-level operations, thereby increasing the efficiency of the processing system.

摘要翻译： 在处理系统中，用于一个或多个存储器设备的集成功能控制器（IFC）包括NAND闪存器件，提供用于将数据写入NAND数据并从NAND闪存器件读取数据的直接存储器访问（DMA）功能，从而减少 支持此类操作所需的CPU干预级别。 在一个实现中，CPU在系统存储器中存储NAND闪存操作的基于描述符的DMA操作序列，然后触发IFC来实现描述符序列。 IFC在不中断CPU或者要求使用例如“重复同时繁忙”轮询描述符类型的任何实时CPU干预的情况下，顺序地获取和实现各个存储的描述符。 IFC释放CPU执行其他系统级操作，从而提高处理系统的效率。

公开(公告)号：US20150380067A1

公开(公告)日：2015-12-31

申请号：US14318685

申请日：2014-06-29

申请人： Prabhjot Singh ,  Hemant Nautiyal ,  Amit Rao

发明人： Prabhjot Singh ,  Hemant Nautiyal ,  Amit Rao

IPC分类号： G11C7/22 ,  G11C7/10

CPC分类号： G11C7/1057 ,  G06F13/1689 ,  G11C7/1066

摘要： A system provides synchronous read data sampling between a memory and a memory controller, which includes an asynchronous FIFO buffer and which outputs a clock and other control signals. An outbound control signal (e.g., read_enable) is used to time-stamp the beginning of a read access using a clock edge counter. The incoming read data is qualified based on the time-stamped value of the read_enable signal plus typical access latency by counting FIFO pops. The system performs correct data sampling irrespective of propagation delays between the controller and memory. The system may be implemented in a System on a Chip (SOC) device having a synchronous communication system.

摘要翻译： 系统提供存储器和存储器控制器之间的同步读取数据采样，存储器控制器包括异步FIFO缓冲器，并输出时钟和其他控制信号。 使用出站控制信号（例如，read_enable）来使用时钟边缘计数器对读取访问的开始进行时间戳。 通过计数FIFO弹出，基于read_enable信号的时间戳值加上典型访问延迟来限定输入读取数据。 系统执行正确的数据采样，而不管控制器和存储器之间的传播延迟。 该系统可以在具有同步通信系统的片上系统（SOC）设备中实现。

公开(公告)号：US20140001158A1

公开(公告)日：2014-01-02

申请号：US13534062

申请日：2012-06-27

申请人： Zhipeng Zhang ,  Andrew Lee Trimmer ,  Mark James Cintula ,  Prabhjot Singh ,  Arvind Rangarajan

发明人： Zhipeng Zhang ,  Andrew Lee Trimmer ,  Mark James Cintula ,  Prabhjot Singh ,  Arvind Rangarajan

IPC分类号： B23H1/04

CPC分类号： B23H1/04 ,  B23H9/10

摘要： A system for repairing a component is provided. The system includes an electrochemical machining unit and a tool delivery apparatus. The electrochemical machining unit includes an electrode, a power supply configured to energize the electrode and the component, and a machining solution source configured to pass a machining solution between the component and the electrode. The tool delivery apparatus includes a number of linkage elements pivotally connected and configured to carry the electrode. The tool delivery apparatus further includes an actuation element configured to actuate the linkage elements to move the electrode. A tool delivery apparatus and a method for repairing a component disposed within a case are also presented.

摘要翻译： 提供了一种用于修复组件的系统。 该系统包括电化学加工单元和工具输送装置。 电化学加工单元包括电极，被配置为使电极和部件通电的电源，以及被配置为在部件和电极之间通过加工溶液的加工液源。 工具传送装置包括枢转地连接和配置为承载电极的多个连接元件。 工具传送装置还包括致动元件，其构造成致动联动元件以移动电极。 还提出了一种用于修理设置在壳体内的部件的工具传送装置和方法。

公开(公告)号：US08611567B2

公开(公告)日：2013-12-17

申请号：US13267610

申请日：2011-10-06

申请人： Matthew Harvey Krohn ,  Prabhjot Singh

发明人： Matthew Harvey Krohn ,  Prabhjot Singh

IPC分类号： H04R25/00 ,  H04R31/00

CPC分类号： B06B1/0629 ,  B06B1/0685 ,  B33Y10/00 ,  B33Y80/00 ,  H04R17/00 ,  H04R31/00 ,  Y10T29/49005

摘要： An acoustic transducer and method of making the acoustic transducer is disclosed. A transducer element for converting a signal between one of an electrical signal and an acoustic signal and the other of the electrical signal and the acoustic signal is provided. A backing to the transducer is additively fabricated to a side of the transducer element. The backing includes an electrically conductive path therein for conducting the electrical signal.

摘要翻译： 公开了一种声学换能器和制造声换能器的方法。 提供了用于转换电信号和声信号之一以及电信号和声信号中的另一个的信号的换能器元件。 传感器的背面被附加地制造到换能器元件的一侧。 背衬包括用于传导电信号的导电路径。

公开(公告)号：US20130076207A1

公开(公告)日：2013-03-28

申请号：US13240754

申请日：2011-09-22

申请人： Matthew Harvey Krohn ,  Prabhjot Singh ,  Paul Aloysius Meyer ,  Wei Luo

发明人： Matthew Harvey Krohn ,  Prabhjot Singh ,  Paul Aloysius Meyer ,  Wei Luo

IPC分类号： H01L41/04 ,  H04R17/00 ,  H01L41/187

CPC分类号： H01L41/183 ,  B06B1/0622 ,  G01N29/245 ,  H01L41/37 ,  Y10T29/42 ,  Y10T29/49002 ,  Y10T29/49005

摘要： A composite ceramic transducer structure for use in the construction of an ultrasound probe includes a substrate and a plurality of piezoelectric transducer posts. The plurality of piezoelectric transducer posts are controllably formed on the substrate in a plurality of spatial positions located on an X-Y plane of the substrate. The plurality of piezoelectric posts includes a plurality of shapes defined in an X-Y-Z plane of the substrate, wherein the plurality of piezoelectric transducer posts are configured to facilitate minimizing shear waves within the ultrasound probe.

摘要翻译： 用于构造超声波探头的复合陶瓷换能器结构包括基底和多个压电传感器柱。 多个压电换能器柱可控制地形成在基板上的位于基板的X-Y平面上的多个空间位置。 所述多个压电柱包括限定在所述基板的X-Y-Z平面中的多个形状，其中所述多个压电换能器柱构造成有助于使所述超声波探头内的剪切波最小化。

公开(公告)号：US20120239961A1

公开(公告)日：2012-09-20

申请号：US13050932

申请日：2011-03-18

申请人： Prakash Makwana ,  Prabhjot Singh

发明人： Prakash Makwana ,  Prabhjot Singh

IPC分类号： G06F1/12

CPC分类号： G06F13/1689

摘要： A synchronous data processing system includes a memory module to store data and a memory controller coupled to the memory module. The memory controller includes a clock inverter to receive an input clock signal and to transmit an inverted clock signal to the memory module. The inverted clock signal incurs a first propagation delay prior to reaching the memory module as a memory clock signal. A write data buffer is coupled to the memory module. The write data buffer transmits data to the memory module in response to the input clock signal. An asynchronous first-in-first-out (ASYNC FIFO) buffer is coupled to the memory module. The ASYNC FIFO buffer reads data from the memory module in response to a feedback signal generated by feeding back the memory clock signal to the ASYNC FIFO buffer.

摘要翻译： 同步数据处理系统包括用于存储数据的存储器模块和耦合到存储器模块的存储器控​​制器。 存储器控制器包括时钟反相器，用于接收输入时钟信号并将反相时钟信号发送到存储器模块。 反向时钟信号在作为存储器时钟信号到达存储器模块之前引起第一传播延迟。 写数据缓冲器耦合到存储器模块。 写数据缓冲器响应于输入时钟信号将数据发送到存储器模块。 异步先入先出（ASYNC FIFO）缓冲器耦合到存储器模块。 ASYNC FIFO缓冲器响应于通过将存储器时钟信号反馈到ASYNC FIFO缓冲器而产生的反馈信号从存储器模块读取数据。

公开(公告)号：US20100149879A1

公开(公告)日：2010-06-17

申请号：US12711520

申请日：2010-02-24

申请人： Hosam Haggag ,  Alexander Kalnitsky ,  Edgardo Laber ,  Prabhjot Singh ,  Michael D. Church

发明人： Hosam Haggag ,  Alexander Kalnitsky ,  Edgardo Laber ,  Prabhjot Singh ,  Michael D. Church

IPC分类号： G11C16/04

CPC分类号： G11C16/0416

摘要： A flash memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a floating gate memory transistor having a source region and a drain region, and a coupling capacitor electrically connected to the memory transistor. A plurality of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the drain region of the memory transistor in each of the memory cells in a respective column. A plurality of high voltage access transistors are each electrically connected to a bit line in the first set of bit lines. A second set of bit lines are each electrically connected to the source region of the memory transistor in each of the memory cells in a respective column. Various combinations of voltages can be applied to the word lines and the first and second sets of bit lines in operations to erase, program, inhibit, or read the logic state stored by the memory transistor in one or more of the memory cells.

摘要翻译： 闪存阵列包括以行和列的矩阵组织的多个存储单元。 每个存储单元包括具有源极区和漏极区的浮动栅极存储晶体管，以及电连接到存储晶体管的耦合电容。 多个字线各自电连接到相应行中的每个存储器单元中的电容器。 第一组位线分别电连接到相应列中的每个存储单元中的存储晶体管的漏极区。 多个高压存取晶体管分别电连接到第一组位线中的位线。 第二组位线分别电连接到相应列中的每个存储器单元中的存储晶体管的源极区域。 在操作中可以对字线和第一和第二组位线施加电压的各种组合，以擦除，编程，禁止或读取存储器晶体管存储在一个或多个存储器单元中的逻辑状态。

公开(公告)号：US07688627B2

公开(公告)日：2010-03-30

申请号：US11861102

申请日：2007-09-25

申请人： Hosam Haggag ,  Alexander Kalnitsky ,  Edgardo Laber ,  Prabhjot Singh ,  Michael D. Church

发明人： Hosam Haggag ,  Alexander Kalnitsky ,  Edgardo Laber ,  Prabhjot Singh ,  Michael D. Church

IPC分类号： G11C14/00 ,  G11C16/04

CPC分类号： G11C16/0416

摘要： A flash memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a floating gate memory transistor having a source region and a drain region, and a coupling capacitor electrically connected to the memory transistor. A plurality of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the drain region of the memory transistor in each of the memory cells in a respective column. A plurality of high voltage access transistors are each electrically connected to a bit line in the first set of bit lines. A second set of bit lines are each electrically connected to the source region of the memory transistor in each of the memory cells in a respective column. Various combinations of voltages can be applied to the word lines and the first and second sets of bit lines in operations to erase, program, inhibit, or read the logic state stored by the memory transistor in one or more of the memory cells.

摘要翻译： 闪存阵列包括以行和列的矩阵组织的多个存储单元。 每个存储单元包括具有源极区和漏极区的浮动栅极存储晶体管，以及电连接到存储晶体管的耦合电容。 多个字线各自电连接到相应行中的每个存储器单元中的电容器。 第一组位线分别电连接到相应列中的每个存储单元中的存储晶体管的漏极区。 多个高压存取晶体管分别电连接到第一组位线中的位线。 第二组位线分别电连接到相应列中的每个存储器单元中的存储晶体管的源极区域。 在操作中可以对字线和第一和第二组位线施加电压的各种组合，以擦除，编程，禁止或读取存储器晶体管存储在一个或多个存储器单元中的逻辑状态。

公开(公告)号：US20090136114A1

公开(公告)日：2009-05-28

申请号：US11945456

申请日：2007-11-27

申请人： Yanyan Wu ,  Francis Howard Little ,  Prabhjot Singh

发明人： Yanyan Wu ,  Francis Howard Little ,  Prabhjot Singh

IPC分类号： G06K9/00

CPC分类号： G06K9/32 ,  G06K9/00 ,  G06K2209/19

摘要： An inspection method is provided and includes acquiring at least one inspection data set. Each inspection data set comprises inspection data for a component. The inspection method further includes mapping the inspection data set onto a three-dimensional (3D) model of the component, to generate a 3D inspection model for the component, and validating the inspection data against the 3D model of the component using at least one validation criterion. A multi-modality inspection method is also provided and includes acquiring multiple inspection data sets corresponding to multiple inspection modalities for a component and fusing the inspection data sets to form a fused data set. The multi-modality inspection method further includes mapping the fused data set onto a 3D model of the component to generate a 3D multi-modality inspection model for the component.

摘要翻译： 提供检查方法，包括获取至少一个检查数据集。 每个检查数据组包括组件的检查数据。 检查方法还包括将检查数据集映射到部件的三维（3D）模型上，以生成用于部件的3D检查模型，并使用至少一个验证来验证检测数据对组件的3D模型 标准。 还提供了一种多模式检查方法，包括获取对应于组件的多个检查模式的多个检查数据集，并将检验数据集合并形成融合数据集。 多模式检查方法还包括将融合数据集映射到组件的3D模型上，以生成用于组件的3D多模态检查模型。