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    Data processing system having centralized memory refresh
    31.
    发明授权
    Data processing system having centralized memory refresh 失效
    数据处理系统具有集中的内存刷新

    公开(公告)号：US4317169A

    公开(公告)日：1982-02-23

    申请号：US12081

    申请日：1979-02-14

    申请人： William Panepinto, Jr. ,  Ming T. Miu ,  Chester M. Nibby, Jr. ,  Jian-Kuo Shen

    发明人： William Panepinto, Jr. ,  Ming T. Miu ,  Chester M. Nibby, Jr. ,  Jian-Kuo Shen

    IPC分类号： G06F12/00 ,  G11C11/406 ,  G06F13/00

    CPC分类号： G11C11/406

    摘要： In a data processing system which includes a central processing unit and one or more main memory units for storing program software instructions and program data, logic is provided within the CPU to signal the main memory units, comprised of semiconductor random access memory chips, that a memory refresh operation can be performed. The logic is organized such that the memory refresh operation signal may be given to the main memory units in parallel with and without detracting from other CPU operations. Further, logic is provided within the CPU to interrupt the CPU normal processing and perform a memory refresh operation if one has not been performed with a predetermined time period. Logic is provided within each main memory unit to accept the memory refresh signals from the CPU and to discard those memory refresh signals that would refresh the memory more frequently than required to retain the memory contents thus reducing main memory power consumption.

    摘要翻译： 在包括中央处理单元和用于存储程序软件指令和程序数据的一个或多个主存储器单元的数据处理系统中，在CPU内提供逻辑以对由半导体随机存取存储器芯片组成的主存储器单元进行信号， 可以执行存储器刷新操作。 逻辑被组织使得可以将存储器刷新操作信号并行并且不降低其他CPU操作的情况下给予主存储器单元。 此外，在CPU内提供中断CPU正常处理的逻辑，并且如果在预定时间段内未执行存储器刷新操作则执行存储器刷新操作。 在每个主存储器单元内提供逻辑以接受来自CPU的存储器刷新信号，并且丢弃将比保持存储器内容所需的频率更新的内存刷新信号，从而减少主存储器功耗的那些存储器刷新信号。

    Power-on sequencing apparatus for initializing and testing a system processing unit
    32.
    发明授权
    Power-on sequencing apparatus for initializing and testing a system processing unit 失效
    用于初始化和测试系统处理单元的上电排序装置

    公开(公告)号：US5491790A

    公开(公告)日：1996-02-13

    申请号：US231856

    申请日：1994-04-22

    申请人： James W. Keeley ,  Richard A. Lemay ,  Chester M. Nibby, Jr. ,  Keith L. Petry ,  Thomas S. Hirsch

    发明人： James W. Keeley ,  Richard A. Lemay ,  Chester M. Nibby, Jr. ,  Keith L. Petry ,  Thomas S. Hirsch

    IPC分类号： G06F1/00 ,  G06F9/06 ,  G06F9/445 ,  G06F11/22 ,  G06F11/267

    CPC分类号： G06F11/2236 ,  G06F11/22 ,  G06F9/4403

    摘要： A processing unit couples to a system bus in common with a peer processor, a main memory, in addition to other units, and includes a microprocessor which tightly couples to a local memory also accessible from such bus. The processing unit also includes an addressable electrically erasable programmable read only memory (EEPROM) unit which is coupled to the microprocessor and the system bus. The EEPROM unit stores in first and second separate regions, both of which occupy the same address space normally allocated for storing the microprocessor's boot code, on-board diagnostic (OBD) routines and operating system boot routines, respectively. EEPROM control circuits at power-up, condition the EEPROM unit to address the first region for executing OBD routines to verify that the processing unit is operating properly, including the ability to properly issue commands to units connected to the system bus. Following loading of the peer processor operating system, the EEPROM control circuits, in response to commands from the system bus, enable the microprocessor to address the second region for executing boot routines for loading its operating system.

    摘要翻译： 除了其他单元之外，处理单元与对等处理器，主存储器共同地耦合到系统总线，并且包括紧密耦合到也可从这样的总线访问的本地存储器的微处理器。 处理单元还包括可寻址的电可擦除可编程只读存储器（EEPROM）单元，其耦合到微处理器和系统总线。 EEPROM单元存储在第一和第二分离区域中，两者分别占据通常分配用于存储微处理器引导代码，车载诊断（OBD）例程和操作系统引导例程的相同地址空间。 EEPROM控制电路在上电时，使EEPROM单元处理第一个区域以执行OBD例程，以验证处理单元是否正常工作，包括正确向连接到系统总线的单元发出命令的能力。 在加载对等处理器操作系统之后，响应于来自系统总线的命令，EEPROM控制电路使得微处理器能够寻址用于执行用于加载其操作系统的引导例程的第二区域。

    Processor bus access
    33.
    发明授权
    Processor bus access 失效
    处理器总线访问

    公开(公告)号：US5341501A

    公开(公告)日：1994-08-23

    申请号：US771582

    申请日：1991-10-04

    申请人： James W. Keeley ,  Richard A. Lemay ,  Chester M. Nibby, Jr.

    发明人： James W. Keeley ,  Richard A. Lemay ,  Chester M. Nibby, Jr.

    IPC分类号： G06F13/368 ,  G06F9/46

    CPC分类号： G06F13/368

    摘要： A high performance microprocessor bus state machine couples to a synchronous local bus in common with another state machine for accessing a local memory according to a preestablished bus protocol. Circuit means cosines the state of a predetermined protocol bus signal indicating the release of the local bus and transitions of the clock signal which are not used for synchronizing the operations of the state machines. The resulting signal applies required address and control signals in advance to the local bus enabling the non-microprocessor state machine to generate the required address strobe to local memory on the next clock which follows the release of the local bus by the microprocessor which eliminates a clock cycle whenever local bus control passes from the microprocessor bus state machine to another state machine.

    摘要翻译： 高性能微处理器总线状态机根据预先建立的总线协议与另一状态机共同连接到同步局部总线，用于访问本地存储器。 电路意味着使指示本地总线的释放和不用于同步状态机的操作的时钟信号的转换的预定的协议总线信号的状态。 所产生的信号预先将所需的地址和控制信号施加到本地总线，使得非微处理器状态机能够在微处理器释放本地总线之后的下一个时钟产生所需的地址选通脉冲，从而消除时钟 当本地总线控制从微处理器总线状态机传递到另一状态机时，循环。

    High speed burst read address generation with high speed transfer
    36.
    发明授权
    High speed burst read address generation with high speed transfer 失效
    高速突发读地址生成与高速传输

    公开(公告)号：US5345573A

    公开(公告)日：1994-09-06

    申请号：US771702

    申请日：1991-10-04

    申请人： Raymond D. Bowden, III ,  Chester M. Nibby, Jr.

    发明人： Raymond D. Bowden, III ,  Chester M. Nibby, Jr.

    IPC分类号： G06F12/08 ,  G06F13/28 ,  G11C11/408 ,  G06F12/00 ,  G11C11/409

    CPC分类号： G06F13/28 ,  G06F12/0879

    摘要： A memory system coupled to a local bus of a microprocessor includes at least a pair of dynamic random access memories (DRAMs) and includes circuits for storing the first address of an address sequence at the beginning of each burst operation and uses predetermined bits to generate any one of a set of address sequences as a function of the states of these bits. A first predetermined address bit is used to select different sequences of addressed readout data words to be transferred by the pair of DRAMs to the user. A second predetermined address bit is complemented to reverse two high order addressed word responses with two low order addressed word responses of specific address sequences. These operations are utilized in all of the required address sequences within different subgroups.

    摘要翻译： 耦合到微处理器的本地总线的存储器系统包括至少一对动态随机存取存储器（DRAM），并且包括用于在每个突发操作开始时存储地址序列的第一地址的电路，并且使用预定位来产生任何 作为这些位的状态的函数的一组地址序列中的一个。 第一预定地址位被用于选择由该对DRAM传送给用户的寻址读出数据字的不同序列。 对第二预定地址位进行补码，以反转具有特定地址序列的两个低阶寻址字响应的两个高阶寻址字应答。 这些操作在不同子组中的所有必需地址序列中使用。

    Remap method and apparatus for a memory system which uses partially good memory devices
    38.
    发明授权
    Remap method and apparatus for a memory system which uses partially good memory devices 失效
    使用部分良好的存储器件的存储器系统的重映射方法和装置

    公开(公告)号：US4527251A

    公开(公告)日：1985-07-02

    申请号：US450691

    申请日：1982-12-17

    申请人： Chester M. Nibby, Jr. ,  Reeni Goldin ,  Timothy A. Andrews

    发明人： Chester M. Nibby, Jr. ,  Reeni Goldin ,  Timothy A. Andrews

    IPC分类号： G06F12/02 ,  G11C29/00 ,  G06F13/00

    CPC分类号： G11C29/76 ,  G06F12/0292

    摘要： A remapping method and apparatus is employed by a memory controller system which includes a microprocessing section which couples to a memory section. The memory section includes a partially good bulk random access memory constructed from a plurality of bit wide chips containing a predefined small number of row or column faults randomly distributed. System columns of chips are organized into a plurality of groups or slices, each of which provide a different predetermined portion of the locations within the partially good bulk memory. A defective-free memory having substantially less capacity is similarly organized. Both memories couple to a static memory which is remapped under the control of the microprocessing section. Prior to remapping, the microprocessing section generates a "slice bit map" indicating the results of testing successive bit groups/slices within the bulk memory locations. Thereafter, the microprocessor section interprets the "slice bit map" and assigns column addresses in the static memory locations designating locations within the defect-free memory. The assignment is carried out in a predetermined manner according to fault category to maximize the use of all of the groups of bit locations within each defect free memory location thereby making storage available for remapping new faults.

    摘要翻译： 存储器控制器系统采用重映射方法和装置，该系统包括耦合到存储器部分的微处理部分。 存储器部分包括由多个位宽的芯片构成的部分良好的批量随机存取存储器，其包含预定义的少量随机分配的行或列故障。 芯片的系统列被组织成多个组或片，每个组或片提供部分良好大容量存储器内的位置的不同预定部分。 类似地组织了具有基本上较小容量的无缺陷存储器。 两个存储器耦合到在微处理部分的控制下重新映射的静态存储器。 在重新映射之前，微处理部分产生指示在大容量存储器位置内测试连续位组/片的结果的“片位图”。 此后，微处理器部分解释“切片位图”，并在无缺陷存储器内指定位置的静态存储单元中分配列地址。 根据故障类别以预定方式执行分配，以最大限度地利用每个无缺陷存储器位置内的所有位组组的使用，从而使存储可用于重新映射新故障。

    Rotating chip selection technique and apparatus
    39.
    发明授权
    Rotating chip selection technique and apparatus 失效
    旋转芯片选择技术和装置

    公开(公告)号：US4296467A

    公开(公告)日：1981-10-20

    申请号：US921292

    申请日：1978-07-03

    申请人： Chester M. Nibby, Jr. ,  William Panepinto, Jr.

    发明人： Chester M. Nibby, Jr. ,  William Panepinto, Jr.

    IPC分类号： G06F12/06 ,  G11C11/407 ,  G11C13/00

    CPC分类号： G11C11/407 ,  G06F12/0669

    摘要： A memory subsystem includes at least one up to a number of memory module boards identical in layout and construction. The board includes a number of memory chips which are positioned at an initial physical row location providing a predetermined number of addressable contiguous memory locations corresponding to a predetermined increment of memory capacity. The board further includes a register for receiving address signals for accessing the contents of a memory location, rotating chip selection circuits which include a set of switches and an arithmetic unit having first and second sets of input terminals. The first set of input terminals is connected to the register for receiving predetermined ones of the address signals representative of the physical row location of chips being addressed and the second set of input terminals are connected to receive signals from the set of switches. The arithmetic unit operates to perform a predetermined arithmetic operation upon the signals applied to the sets of input terminals to generate a set of logical row address signals for enabling the number of chips at the initial row location.

    摘要翻译： 存储器子系统包括至少一个在布局和结构上相同的多个存储器模块板。 该板包括多个存储器芯片，这些存储器芯片位于初始物理行位置，提供对应于预定增量的存储器容量的预定数量的可寻址连续存储器位置。 板还包括一个寄存器，用于接收访问存储器位置的内容的地址信号，旋转芯片选择电路包括一组开关和具有第一组和第二组输入端的运算单元。 第一组输入端子连接到寄存器，用于接收表示正在寻址的芯片的物理行位置的预定的地址信号，并且第二组输入端子被连接以从该组开关接收信号。 算术单元操作以对施加到输入端子组的信号执行预定的算术运算，以产生用于使初始行位置处的码片数量的一组逻辑行地址信号。