公开(公告)号：US09786765B2

公开(公告)日：2017-10-10

申请号：US15044431

申请日：2016-02-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Edward J. Nowak ,  Brent A. Anderson ,  Andreas Scholze

IPC: H01L29/78 ,  H01L29/06 ,  H01L21/762 ,  H01L29/66 ,  H01L21/28

CPC classification number: H01L29/66545 ,  H01L21/28079 ,  H01L29/66795 ,  H01L29/785

Abstract: One aspect of the disclosure provides for a method of forming a replacement gate structure. The method may include: removing a dummy gate from over a set of fins to form an opening in a dielectric layer exposing the set of fins, each fin in the set of fins being substantially separated from an adjacent fin in the set of fins via an dielectric; forming a protective cap layer within the opening over the exposed set of fins; removing a portion of the dielectric on each side of each fin in the set of fins; undercutting each fin by removing a portion of each fin in the set of fins to create a notch disposed under the protective cap layer; substantially filling each notch with an oxide; forming a gate dielectric over each fin in the set of fins; and forming a gate conductor over the gate dielectric, thereby forming the replacement gate structure.

公开(公告)号：US09659941B2

公开(公告)日：2017-05-23

申请号：US14754958

申请日：2015-06-30

Applicant: GLOBALFOUNDRIES INC.

Inventor： Brent A. Anderson ,  Edward J. Nowak

IPC: H01L27/11 ,  H01L21/28 ,  H01L29/417 ,  H01L27/12 ,  H01L29/45

CPC classification number: H01L27/1104 ,  H01L21/28008 ,  H01L27/1211 ,  H01L29/41791 ,  H01L29/45

Abstract: Embodiments of the present disclosure provide an integrated circuit (IC) structure and methods of electrically connecting multiple IC structures. An IC structure according to embodiments of the present disclosure can include: a first conductive region; a second conductive region laterally separated from the first conductive region; a first vertically-oriented semiconductor fin formed over and contacting the first conductive region; a second vertically-oriented semiconductor fin formed over and contacting the second conductive region; and a first gate contacting each of the first vertically-oriented semiconductor fin and the second conductive region, wherein the first gate includes: a substantially horizontal section contacting the first vertically-oriented semiconductor fin, and a substantially vertical section contacting the second conductive region.

公开(公告)号：US09613861B2

公开(公告)日：2017-04-04

申请号：US14818419

申请日：2015-08-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Brent A. Anderson ,  Edward J. Nowak

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/528

CPC classification number: H01L21/76897 ,  H01L21/76883 ,  H01L21/76885 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53238

Abstract: Damascene wires with top via structures and methods of manufacture are provided. The semiconductor structure includes a damascene wiring structure with an integrally formed top via structure in self-alignment with the damascene wiring structure which is underneath the integrally formed top via structure.

公开(公告)号：US09536882B2

公开(公告)日：2017-01-03

申请号：US14574504

申请日：2014-12-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Brent A. Anderson ,  Edward J. Nowak ,  Robert R. Robison ,  Andreas Scholze

IPC: H01L27/092 ,  H01L21/8238 ,  H01L21/3213 ,  H01L21/321 ,  H01L29/10

CPC classification number: H01L27/0924 ,  H01L21/32115 ,  H01L21/32133 ,  H01L21/823821 ,  H01L21/823871 ,  H01L21/823892 ,  H01L27/0928 ,  H01L29/1087

Abstract: Disclosed are isolation techniques for bulk FinFETs. A semiconductor device includes a semiconductor substrate with a fin structure on the semiconductor substrate. The fin structure is perpendicular to the semiconductor substrate and has an upper portion and a lower portion. Source and drain regions are adjacent to the fin structure. A gate structure surrounds the upper portion of the fin structure. A well contact point is provided in the semiconductor substrate. The lower portion of the fin structure includes a sub-fin between the region surrounded by the gate structure and the semiconductor substrate. The sub-fin directly contacts the semiconductor substrate. The upper portion of the fin structure and an upper portion of the sub-fin are undoped. A lower portion of the sub-fin may be doped. Electrical potential applied from the well contact point to the lower portion of the sub-fin reduces leakage currents from the upper portion of the fin structure.

Abstract translation: 公开了用于散装FinFET的隔离技术。 半导体器件包括在半导体衬底上具有翅片结构的半导体衬底。 翅片结构垂直于半导体衬底并具有上部和下部。 源极和漏极区域与翅片结构相邻。 栅极结构围绕鳍结构的上部。 在半导体衬底中提供良好的接触点。 翅片结构的下部包括在被栅极结构包围的区域和半导体衬底之间的子鳍。 子鳍直接接触半导体衬底。 翅片结构的上部和副翅片的上部是未掺杂的。 子鳍片的下部可以被掺杂。 从阱接触点施加到副散热片的下部的电势减小了从翅片结构的上部的泄漏电流。

公开(公告)号：US20160380065A1

公开(公告)日：2016-12-29

申请号：US15263551

申请日：2016-09-13

Applicant: GlobalFoundries Inc.

Inventor： Brent A. Anderson ,  Jeffrey B. Johnson ,  Edward J. Nowak

IPC: H01L29/417 ,  H01L29/66 ,  H01L29/08 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L23/5283 ,  H01L21/76816 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/535 ,  H01L29/0847 ,  H01L29/41775 ,  H01L29/66484 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7831 ,  H01L29/7851

Abstract: Disclosed are semiconductor structures comprising a field effect transistor (FET) having a low-resistance source/drain contact and, optionally, low gate-to-source/drain contact capacitance. The structures comprise a semiconductor body and, contained therein, first and second source/drain regions and a channel region. A first gate is adjacent to the semiconductor body at the channel region and a second, non-functioning, gate is adjacent to the semiconductor body such that the second source/drain region is between the first and second gates. First and second source/drain contacts are on the first and source/drain regions, respectively. The second source/drain contact is wider than the first and, thus, has a lower resistance. Additionally, spacing of the first and second source/drain contacts relative to the first gate can be such that the first gate-to-second source/drain contact capacitance is equal to or less than the first gate-to-first source/drain contact capacitance. Also disclosed are associated formation methods.

公开(公告)号：US09436789B2

公开(公告)日：2016-09-06

申请号：US14517292

申请日：2014-10-17

Applicant: GLOBALFOUNDRIES INC.

Inventor： Brent A. Anderson ,  Edward J. Nowak ,  Jed H. Rankin

IPC: G06F17/50 ,  H01L27/12 ,  H01L21/8234 ,  H01L27/02 ,  H01L27/088 ,  H01L27/092 ,  H01L21/8228 ,  H01L21/8238 ,  H01L21/84

CPC classification number: G06F17/5072 ,  G06F17/5081 ,  H01L21/8228 ,  H01L21/823412 ,  H01L21/8238 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/1203

Abstract: A structure, method and system for complementary strain fill for integrated circuit chips. The structure includes a first region of an integrated circuit having multiplicity of n-channel and p-channel field effect transistors (FETs); a first stressed layer over n-channel field effect transistors (NFETs) of the first region, the first stressed layer of a first stress type; a second stressed layer over p-channel field effect transistors (PFETs) of the first region, the second stressed layer of a second stress type, the second stress type opposite from the first stress type; and a second region of the integrated circuit, the second region not containing FETs, the second region containing first sub-regions of the first stressed layer and second sub-regions of the second stressed layer.