公开(公告)号：US20140017862A1

公开(公告)日：2014-01-16

申请号：US14028957

申请日：2013-09-17

Applicant: Globalfoundries Inc. ,  International Business Machines Corporation

Inventor： Jian Yu ,  Jeffrey B. Johnson ,  Zhengwen Li ,  Chengwen Pei ,  Michael Hargrove

IPC: H01L29/66

CPC classification number: H01L29/66477 ,  H01L21/28518 ,  H01L21/76814 ,  H01L21/76831 ,  H01L23/485 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a semiconductor device is provided that includes forming a gate structure on a channel portion of a semiconductor substrate, forming an interlevel dielectric layer over the gate structure, and forming a opening through the interlevel dielectric layer to an exposed surface of the semiconductor substrate containing at least one of the source region and the drain region. A metal semiconductor alloy contact is formed on the exposed surface of the semiconductor substrate. At least one dielectric sidewall spacer is formed on sidewalls of the opening. An interconnect is formed within the opening in direct contact with the metal semiconductor alloy contact.

Abstract translation: 提供一种形成半导体器件的方法，包括在半导体衬底的沟道部分上形成栅极结构，在栅极结构上方形成层间电介质层，并通过层间介质层形成通向半导体的暴露表面的开口 含有源区和漏区中的至少一个的衬底。 在半导体衬底的暴露表面上形成金属半导体合金接触。 在开口的侧壁上形成至少一个电介质侧壁间隔物。 在与金属半导体合金接触件直接接触的开口内形成互连。

公开(公告)号：US10403772B2

公开(公告)日：2019-09-03

申请号：US15886927

申请日：2018-02-02

Applicant: GLOBALFOUNDRIES INC.

Inventor： Juntao Li ,  Kangguo Cheng ,  Chengwen Pei ,  Geng Wang ,  Joseph Ervin

IPC: G02B6/12 ,  H01L31/0232 ,  H01L23/48 ,  G02B6/42 ,  G02B6/43 ,  G02B6/122 ,  H01L31/02 ,  H01L21/768

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to electrical and optical via connections on a same chip and methods of manufacture. The structure includes an optical through substrate via (TSV) comprising an optical material filling the TSV. The structure further includes an electrical TSV which includes a liner of the optical material and a conductive material filling remaining portions of the electrical TSV.

公开(公告)号：US10224418B2

公开(公告)日：2019-03-05

申请号：US15793419

申请日：2017-10-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Chengwen Pei ,  Xusheng Wu ,  Ziyan Xu

IPC: H01L23/48 ,  H01L29/66 ,  H01L21/22 ,  H01L21/225 ,  H01L21/285 ,  H01L29/78 ,  H01L29/207 ,  H01L21/311

Abstract: Aspects of the present disclosure include fabricating integrated circuit (IC) structures using a boron etch-stop layer, and IC structures with a boron-rich region therein. Methods of forming an IC structure according to the present disclosure can include: growing a conductive epitaxial layer on an upper surface of a semiconductor element; forming a boron etch-stop layer directly on an upper surface of the conductive epitaxial layer; forming an insulator on the boron etch-stop layer; forming an opening within the insulator to expose an upper surface of the boron etch-stop layer; annealing the boron etch-stop layer to drive boron into the conductive epitaxial layer, such that the boron etch-stop layer becomes a boron-rich region; and forming a contact to the boron-rich region within the opening, such that the contact is electrically connected to the semiconductor element through at least the conductive epitaxial layer.

公开(公告)号：US20180204796A1

公开(公告)日：2018-07-19

申请号：US15408883

申请日：2017-01-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Geng Wang ,  Kangguo Cheng ,  Chengwen Pei ,  Juntao Li

IPC: H01L23/522 ,  H01L49/02 ,  H01L21/822 ,  H01L23/528 ,  H01L21/768

CPC classification number: H01L23/5223 ,  H01L21/76805 ,  H01L21/8221 ,  H01L23/5226 ,  H01L23/5283 ,  H01L28/60

Abstract: Various embodiments include three-dimensional (3D) integrated circuit (IC) structures and methods of forming such structures. In some cases, a 3D IC structure includes: a substrate; a first set of transistors overlying the substrate; a first inter-level dielectric (ILD) overlying the first set of transistors and the substrate; a dielectric overlying the first ILD; a semiconductor layer overlying the dielectric; a second set of transistors overlying the semiconductor layer; a capacitor embedded within the dielectric; and a first contact extending through the semiconductor layer and the dielectric to contact one layer of the capacitor, and a second contact extending through the semiconductor layer and the dielectric to contact a second, distinct layer of the capacitor.

公开(公告)号：US09960226B2

公开(公告)日：2018-05-01

申请号：US15661504

申请日：2017-07-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Wai-Kin Li ,  Chengwen Pei ,  Ping-Chuan Wang

IPC: H01L49/02 ,  H01L21/8238 ,  H01L27/06

CPC classification number: H01L28/92 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/0629

Abstract: High density capacitor structures based on an array of semiconductor nanorods are provided. The high density capacitor structure can be a plurality of capacitors in which each of the semiconductor nanorods serves as a bottom electrode for one of the plurality of capacitors, or a large-area metal-insulator-metal (MIM) capacitor in which the semiconductor nanorods serve as a support structure for a bottom electrode of the MIM capacitor subsequently formed.

公开(公告)号：US20170373005A1

公开(公告)日：2017-12-28

申请号：US15189432

申请日：2016-06-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chengwen Pei ,  Kangguo Cheng ,  Juntao Li ,  Geng Wang

IPC: H01L23/525 ,  H01L29/06 ,  H01L21/265 ,  H01L27/112 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L23/5252 ,  H01L21/265 ,  H01L27/11206 ,  H01L29/0649 ,  H01L29/66795 ,  H01L29/785

Abstract: Device structures for an anti-fuse and methods for manufacturing device structures for an anti-fuse. The anti-fuse includes a first terminal comprised of a fin. The fin includes a section with an edge and inclined surfaces that intersect at the edge. The anti-fuse further includes a second terminal covering the edge and the inclined surfaces of the fin, and an isolation dielectric layer on the inclined surfaces and the edge of the fin. The second terminal is separated from the edge and inclined surfaces of the fin by the isolation dielectric layer. The edge and inclined surfaces on the firm may be formed by oxidizing an upper section of the fin in a trench to form an oxide layer, and then removing the oxide layer to expose the edge and inclined surfaces.

公开(公告)号：US09852982B1

公开(公告)日：2017-12-26

申请号：US15189432

申请日：2016-06-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chengwen Pei ,  Kangguo Cheng ,  Juntao Li ,  Geng Wang

IPC: H01L23/52 ,  H01L23/525 ,  H01L29/78 ,  H01L27/112 ,  H01L29/06 ,  H01L29/66 ,  H01L21/265

CPC classification number: H01L23/5252 ,  H01L21/265 ,  H01L27/11206 ,  H01L29/0649 ,  H01L29/66795 ,  H01L29/785

Abstract: Device structures for an anti-fuse and methods for manufacturing device structures for an anti-fuse. The anti-fuse includes a first terminal comprised of a fin. The fin includes a section with an edge and inclined surfaces that intersect at the edge. The anti-fuse further includes a second terminal covering the edge and the inclined surfaces of the fin, and an isolation dielectric layer on the inclined surfaces and the edge of the fin. The second terminal is separated from the edge and inclined surfaces of the fin by the isolation dielectric layer. The edge and inclined surfaces on the firm may be formed by oxidizing an upper section of the fin in a trench to form an oxide layer, and then removing the oxide layer to expose the edge and inclined surfaces.

公开(公告)号：US20170358691A1

公开(公告)日：2017-12-14

申请号：US15181834

申请日：2016-06-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kai Xiu ,  Chengwen Pei ,  Pinping Sun

IPC: H01L29/93 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H03L7/093 ,  H03L7/099

Abstract: Various particular embodiments include a semiconductor varactor structure including: a semiconductor substrate of a first conductivity type; a semiconductor area of a second conductivity type, different from the first conductivity type, within the semiconductor substrate; a field effect transistor (FET) structure within the semiconductor area; and a contact, contacting the semiconductor area, for applying a voltage bias to the semiconductor area.

公开(公告)号：US09842913B1

公开(公告)日：2017-12-12

申请号：US15157868

申请日：2016-05-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Chengwen Pei ,  Xusheng Wu ,  Ziyan Xu

IPC: H01L21/70 ,  H01L29/66 ,  H01L29/78 ,  H01L21/285 ,  H01L21/22 ,  H01L21/225 ,  H01L21/311 ,  H01L29/207

CPC classification number: H01L29/66795 ,  H01L21/2225 ,  H01L21/2254 ,  H01L21/28518 ,  H01L21/31144 ,  H01L29/207 ,  H01L29/66545 ,  H01L29/7845 ,  H01L29/7848 ,  H01L29/785

Abstract: Aspects of the present disclosure include fabricating integrated circuit (IC) structures using a boron etch-stop layer, and IC structures with a boron-rich region therein. Methods of forming an IC structure according to the present disclosure can include: growing a conductive epitaxial layer on an upper surface of a semiconductor element; forming a boron etch-stop layer directly on an upper surface of the conductive epitaxial layer; forming an insulator on the boron etch-stop layer; forming an opening within the insulator to expose an upper surface of the boron etch-stop layer; annealing the boron etch-stop layer to drive boron into the conductive epitaxial layer, such that the boron etch-stop layer becomes a boron-rich region; and forming a contact to the boron-rich region within the opening, such that the contact is electrically connected to the semiconductor element through at least the conductive epitaxial layer.

公开(公告)号：US20170323937A1

公开(公告)日：2017-11-09

申请号：US15661504

申请日：2017-07-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Wai-Kin Li ,  Chengwen Pei ,  Ping-Chuan Wang

IPC: H01L49/02 ,  H01L21/8238 ,  H01L27/06

CPC classification number: H01L28/92 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/0629

Abstract: High density capacitor structures based on an array of semiconductor nanorods are provided. The high density capacitor structure can be a plurality of capacitors in which each of the semiconductor nanorods serves as a bottom electrode for one of the plurality of capacitors, or a large-area metal-insulator-metal (MIM) capacitor in which the semiconductor nanorods serve as a support structure for a bottom electrode of the MIM capacitor subsequently formed.