公开(公告)号：US10770454B2

公开(公告)日：2020-09-08

申请号：US15948609

申请日：2018-04-09

Applicant: GLOBALFOUNDRIES INC.

Inventor： Chanro Park ,  Ruilong Xie ,  Kangguo Cheng ,  Juntao Li

IPC: H01L27/108 ,  H01L27/06 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/762 ,  H01L49/02

Abstract: We report a semiconductor device, containing a semiconductor substrate; an isolation feature on the substrate; a plurality of gates on the isolation feature, wherein each gate comprises a gate electrode and a high-k dielectric layer disposed between the gate electrode and the isolation feature and disposed on and in contact with at least one side of the gate electrode; and a fill metal between the plurality of gates on the isolation feature. We also report methods of forming such a device, and a system for manufacturing such a device.

公开(公告)号：US20190312028A1

公开(公告)日：2019-10-10

申请号：US15948609

申请日：2018-04-09

Applicant: GLOBALFOUNDRIES INC.

Inventor： Chanro Park ,  Ruilong Xie ,  Kangguo Cheng ,  Juntao Li

IPC: H01L27/06 ,  H01L29/78 ,  H01L49/02 ,  H01L21/762 ,  H01L21/8234

Abstract: We report a semiconductor device, containing a semiconductor substrate; an isolation feature on the substrate; a plurality of gates on the isolation feature, wherein each gate comprises a gate electrode and a high-k dielectric layer disposed between the gate electrode and the isolation feature and disposed on and in contact with at least one side of the gate electrode; and a fill metal between the plurality of gates on the isolation feature. We also report methods of forming such a device, and a system for manufacturing such a device.

公开(公告)号：US09490223B2

公开(公告)日：2016-11-08

申请号：US14566773

申请日：2014-12-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Joseph Ervin ,  Juntao Li ,  Chengwen Pei ,  Geng Wang

IPC: H01L21/70 ,  H01L23/00 ,  H01L29/06 ,  H01L21/762

CPC classification number: H01L23/564 ,  H01L21/26586 ,  H01L21/743 ,  H01L21/76229 ,  H01L21/84 ,  H01L29/0646 ,  H01L29/0649 ,  H01L29/66181 ,  H01L29/945 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure is provided that includes a semiconductor on insulator (SOI) substrate comprising a bottom semiconductor layer, an epitaxial semiconductor layer present on the bottom semiconductor layer, a buried insulator layer present on the epitaxial semiconductor layer, and a top semiconductor layer present on the buried insulator layer. A deep trench moat (DTMOAT) is disposed in the SOI substrate and has a bottom surface contacting a dopant region of the bottom semiconductor layer. A moat contact electrically connecting the DTMOAT to the epitaxial semiconductor layer of the SOI substrate. Charges accumulated in the DTMOAT can be discharged through the heavily doped epitaxial semiconductor layer to ground, thus preventing the DTMOAT failure caused by the process-induced charge accumulation.

Abstract translation: 提供一种半导体结构，其包括半导体绝缘体（SOI）衬底，其包括底部半导体层，存在于底部半导体层上的外延半导体层，存在于外延半导体层上的掩埋绝缘体层以及存在于外部半导体层上的顶部半导体层 埋层绝缘体层。 深沟槽沟（DTMOAT）设置在SOI衬底中并具有与底部半导体层的掺杂区接触的底面。 将DTMOAT电连接到SOI衬底的外延半导体层的护套接点。 在DTMOAT中累积的电荷可以通过重掺杂的外延半导体层放电到地面，从而防止由过程引起的电荷积累引起的DTMOAT故障。

公开(公告)号：US09105617B2

公开(公告)日：2015-08-11

申请号：US14079043

申请日：2013-11-13

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machine Corporation

Inventor： Ruilong Xie ,  Shom Ponoth ,  Juntao Li

IPC: H01L21/02 ,  H01L29/49 ,  H01L27/085

CPC classification number: H01L27/088 ,  H01L21/823437 ,  H01L21/823828 ,  H01L27/0207 ,  H01L27/085 ,  H01L27/092 ,  H01L29/0692 ,  H01L29/42372 ,  H01L29/4916 ,  H01L29/66628

Abstract: One method disclosed herein includes, among other things, forming a line-end protection layer in an opening on an entirety of each opposing, spaced-apart first and second end face surfaces of first and second spaced-apart gate electrode structures, respectively, and forming a sidewall spacer adjacent opposing sidewall surfaces of each of the gate electrode structures but not adjacent the opposing first and second end face surfaces having the line-end protection layer positioned thereon.

Abstract translation: 本文公开的一种方法包括分别在第一和第二间隔开的栅电极结构的每个相对的间隔开的第一和第二端面表面的整个开口中的开口中形成线端保护层，以及 形成邻近每个栅极电极结构的相对侧壁表面的侧壁间隔件，但不邻近具有定位在其上的线端保护层的相对的第一和第二端面表面。

公开(公告)号：US11069677B2

公开(公告)日：2021-07-20

申请号：US16941423

申请日：2020-07-28

Applicant: GLOBALFOUNDRIES INC.

Inventor： Chanro Park ,  Ruilong Xie ,  Kangguo Cheng ,  Juntao Li

IPC: H01L27/108 ,  H01L27/06 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/762 ,  H01L49/02

Abstract: We report a semiconductor device, containing a semiconductor substrate; an isolation feature on the substrate; a plurality of gates on the isolation feature, wherein each gate comprises a gate electrode and a high-k dielectric layer disposed between the gate electrode and the isolation feature and disposed on and in contact with at least one side of the gate electrode; and a fill metal between the plurality of gates on the isolation feature. We also report methods of forming such a device, and a system for manufacturing such a device.

公开(公告)号：US10388732B1

公开(公告)日：2019-08-20

申请号：US15992942

申请日：2018-05-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Julien Frougier ,  Ruilong Xie ,  Nicolas Loubet ,  Kangguo Cheng ,  Juntao Li

IPC: H01L29/06 ,  H01L29/786 ,  H01L29/08 ,  H01L29/423 ,  H01L29/24 ,  H01L29/16 ,  H01L21/02 ,  H01L21/04 ,  H01L29/66 ,  H01L21/423 ,  H01L21/441 ,  H01L29/10

Abstract: Structures for a field-effect transistor and methods of forming structures for a field-effect transistor. A plurality of channel layers are arranged in a layer stack, and a source/drain region is connected with the plurality of channel layers. A gate structure includes a plurality of sections that respectively surround the plurality of channel layers. The plurality of channel layers contain a two-dimensional semiconducting material.

公开(公告)号：US10290574B2

公开(公告)日：2019-05-14

申请号：US15408883

申请日：2017-01-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Geng Wang ,  Kangguo Cheng ,  Chengwen Pei ,  Juntao Li

IPC: H01L23/522 ,  H01L49/02 ,  H01L21/822 ,  H01L23/528 ,  H01L21/768

Abstract: Various embodiments include three-dimensional (3D) integrated circuit (IC) structures and methods of forming such structures. In some cases, a 3D IC structure includes: a substrate; a first set of transistors overlying the substrate; a first inter-level dielectric (ILD) overlying the first set of transistors and the substrate; a dielectric overlying the first ILD; a semiconductor layer overlying the dielectric; a second set of transistors overlying the semiconductor layer; a capacitor embedded within the dielectric; and a first contact extending through the semiconductor layer and the dielectric to contact one layer of the capacitor, and a second contact extending through the semiconductor layer and the dielectric to contact a second, distinct layer of the capacitor.

公开(公告)号：US20160071928A1

公开(公告)日：2016-03-10

申请号：US14943522

申请日：2015-11-17

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Ruilong Xie ,  Shom Ponoth ,  Juntao Li

IPC: H01L29/06 ,  H01L29/423 ,  H01L27/088 ,  H01L29/78

CPC classification number: H01L29/0649 ,  H01L21/28008 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/42356 ,  H01L29/66545 ,  H01L29/785

Abstract: A transistor device includes first and second spaced-apart active regions positioned in a semiconductor substrate, each of the respective first and second spaced-apart active regions having at least one fin. First and second spaced-apart gate structures are positioned above the respective first and second active regions, each of the first and second gate structures having end surfaces. A gate separation structure is positioned between the first and second spaced-apart gate structures, wherein first and second opposing surfaces of the gate separation structure abut an entirety of the respective end surfaces of the first and second spaced-apart gate structures, and wherein an upper surface of the gate separation structure is positioned at a greater height level above the semiconductor substrate than an upper surface of the at least one fin of each of the respective first and second spaced-apart active regions.

Abstract translation: 晶体管器件包括位于半导体衬底中的第一和第二间隔开的有源区，相应的第一和第二间隔开的有源区中的每一个具有至少一个鳍。 第一和第二间隔开的栅极结构位于相应的第一和第二有源区域的上方，第一和第二栅极结构中的每一个具有端面。 栅极分离结构位于第一和第二间隔开的栅极结构之间，其中栅极分离结构的第一和第二相对表面邻接第一和第二间隔开的栅极结构的相应端表面的整体，并且其中 栅极分离结构的上表面位于比半导体衬底的每个相应的第一和第二间隔开的有源区的至少一个鳍的上表面更高的高度上。

公开(公告)号：US09219153B2

公开(公告)日：2015-12-22

申请号：US13972348

申请日：2013-08-21

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Ruilong Xie ,  Shom Ponoth ,  Juntao Li

IPC: H01L21/336 ,  H01L29/78 ,  H01L21/28 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/66 ,  H01L27/092 ,  H01L27/12

CPC classification number: H01L29/0649 ,  H01L21/28008 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/42356 ,  H01L29/66545 ,  H01L29/785

Abstract: One method disclosed herein includes forming a stack of material layers to form gate structures, performing a first etching process to define an opening through the stack of materials that defines an end surface of the gate structures, forming a gate separation structure in the opening and performing a second etching process to define side surfaces of the gate structures. A device disclosed herein includes first and second active regions that include at least one fin, first and second gate structures, wherein each of the gate structures have end surfaces, and a gate separation structure positioned between the gate structures, wherein opposing surfaces of the gate separation structure abut the end surfaces of the gate structures, and wherein an upper surface of the gate separation structure is positioned above an upper surface of the at least one fin.

Abstract translation: 本文公开的一种方法包括形成堆叠的材料层以形成栅极结构，执行第一蚀刻工艺以通过限定栅极结构的端面的材料层限定开口，在开口中形成栅极分离结构并执行 用于限定栅极结构的侧表面的第二蚀刻工艺。 本文公开的装置包括第一和第二有源区，其包括至少一个鳍状，第一和第二栅极结构，其中每个栅极结构具有端面，以及位于栅极结构之间的栅极分离结构，其中栅极的相对表面 分离结构邻接门结构的​​端面，并且其中门分离结构的上表面位于至少一个翅片的上表面上方。

公开(公告)号：US20160172314A1

公开(公告)日：2016-06-16

申请号：US14566773

申请日：2014-12-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Joseph Ervin ,  Juntao Li ,  Chengwen Pei ,  Geng Wang

IPC: H01L23/00 ,  H01L21/762 ,  H01L29/06

CPC classification number: H01L23/564 ,  H01L21/26586 ,  H01L21/743 ,  H01L21/76229 ,  H01L21/84 ,  H01L29/0646 ,  H01L29/0649 ,  H01L29/66181 ,  H01L29/945 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure is provided that includes a semiconductor on insulator (SOI) substrate comprising a bottom semiconductor layer, an epitaxial semiconductor layer present on the bottom semiconductor layer, a buried insulator layer present on the epitaxial semiconductor layer, and a top semiconductor layer present on the buried insulator layer. A deep trench moat (DTMOAT) is disposed in the SOI substrate and has a bottom surface contacting a dopant region of the bottom semiconductor layer. A moat contact electrically connecting the DTMOAT to the epitaxial semiconductor layer of the SOI substrate. Charges accumulated in the DTMOAT can be discharged through the heavily doped epitaxial semiconductor layer to ground, thus preventing the DTMOAT failure caused by the process-induced charge accumulation.

Abstract translation: 提供一种半导体结构，其包括半导体绝缘体（SOI）衬底，其包括底部半导体层，存在于底部半导体层上的外延半导体层，存在于外延半导体层上的掩埋绝缘体层以及存在于外部半导体层上的顶部半导体层 埋层绝缘体层。 深沟槽沟（DTMOAT）设置在SOI衬底中并具有与底部半导体层的掺杂区接触的底面。 将DTMOAT电连接到SOI衬底的外延半导体层的护套接点。 在DTMOAT中累积的电荷可以通过重掺杂的外延半导体层放电到地面，从而防止由过程引起的电荷积累引起的DTMOAT故障。