公开(公告)号：US10651281B1

公开(公告)日：2020-05-12

申请号：US16207915

申请日：2018-12-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Siva P. Adusumilli ,  John J. Ellis-Monaghan ,  Anthony K. Stamper ,  Ian McCallum-Cook ,  Mark Goldstein

IPC: H01L29/32 ,  H01L29/66 ,  H01L29/786 ,  H01L21/265 ,  C23C16/48 ,  H01L21/762 ,  C23C16/40 ,  H01L29/04 ,  H01L21/266

Abstract: Structures with altered crystallinity beneath semiconductor devices and methods associated with forming such structures. A semiconductor layer is implanted over a first depth range of an inert gas species to modify the crystal structure of a semiconductor material of the semiconductor layer and form a first modified region. The semiconductor layer is annealed with a first annealing process to convert the semiconductor material within the first modified region to a non-single-crystal layer. The semiconductor layer is also implanted with ions of an element over a second depth range to modify the crystal structure of the semiconductor material of the semiconductor layer and form a second modified region containing a concentration of the element. The semiconductor layer is annealed with a second annealing process to convert the semiconductor material within the second modified region to an insulator layer containing the element.

公开(公告)号：US20200144404A1

公开(公告)日：2020-05-07

申请号：US16177877

申请日：2018-11-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Joshua Dillon ,  Siva P. Adusumilli ,  Jagar Singh ,  Anthony Stamper ,  Laura Schutz

IPC: H01L29/76 ,  H01L29/66 ,  H01L29/872

Abstract: One device disclosed herein includes, among other things, first and second conductive features embedded in a first dielectric layer, a cap layer positioned above the first dielectric layer, a ballistic transport material contacting the first conductive member and positioned above a portion of the first dielectric layer, and first and second contacts contacting the first and second conductive features.

公开(公告)号：US20180350659A1

公开(公告)日：2018-12-06

申请号：US15609742

申请日：2017-05-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Siva P. Adusumilli ,  Steven M. Shank ,  Richard A. Phelps ,  Anthony K. Stamper

IPC: H01L21/762

CPC classification number: H01L21/76229 ,  H01L21/0262 ,  H01L21/76235 ,  H01L21/7624

Abstract: Structures for shallow trench isolation regions and methods for forming shallow trench isolation regions. A trench is etched partially through a device layer of a silicon-on-insulator substrate. A section of the device layer at a bottom of the trench is thermally oxidized to form a shallow trench isolation region in the trench. During the thermal oxidation, another region of the device layer may be concurrently oxidized over a partial thickness and, after removal of the oxide from this device layer region, used as a thinned silicon body. Prior to the thermal oxidation process, this device layer region may be implanted with an oxidation-retarding species that decreases its oxidation rate in comparison with the oxidation rate of the section of the device layer used to form the shallow trench isolation region.

公开(公告)号：US09984936B1

公开(公告)日：2018-05-29

申请号：US15651621

申请日：2017-07-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Siva P. Adusumilli ,  Kangguo Cheng ,  Pietro Montanini ,  Robinhsinku Chao

IPC: H01L21/8234 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L21/823481 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/785

Abstract: A method includes forming a sacrificial gate and a stack of materials above a semiconductor substrate, forming a trench in each of the source/drain areas of the device, wherein each trench extends into the semiconductor substrate, forming an empty space under the sacrificial gate structure, the empty space being vertically positioned between the stack of materials and the semiconductor substrate, wherein the empty space is in communication with the trenches, performing a conformal deposition process so as to deposit a conformal layer of a device isolation material adjacent at least the sacrificial gate while at least partially filling the empty space and substantially filling the trenches, and performing a recess etching process to remove at least portions of the conformal layer positioned adjacent the sacrificial gate, thereby defining a recessed upper surface of the device isolation material.