公开(公告)号：US09842184B2

公开(公告)日：2017-12-12

申请号：US15047878

申请日：2016-02-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anurag Mittal ,  Mahbub Rashed

IPC: G06F17/50 ,  H01L23/00 ,  H01L27/00 ,  H01L27/12 ,  H01L27/02 ,  H01L23/528

CPC classification number: G06F17/5072 ,  G06F17/5077 ,  G06F17/5081 ,  G06F2217/78 ,  G06F2217/84 ,  H01L21/84 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/1203

Abstract: At least one method, apparatus and system disclosed involves providing a design for manufacturing a semiconductor device. A first functional cell having a first width is placed on a circuit layout. A determination is made as to whether at least one transistor of the first functional cell is to be forward biased or reversed biased. A second functional cell having a second width is placed adjacent to the first functional cell on the circuit layout for providing a first biasing well within the total width of the first and second functional cells in response to determining that the at least one transistor is to be forward biased or reversed biased.

公开(公告)号：US20170076031A1

公开(公告)日：2017-03-16

申请号：US15047878

申请日：2016-02-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anurag Mittal ,  Mahbub Rashed

IPC: G06F17/50 ,  H01L27/02 ,  H01L23/528 ,  H01L27/12

CPC classification number: G06F17/5072 ,  G06F17/5077 ,  G06F17/5081 ,  G06F2217/78 ,  G06F2217/84 ,  H01L21/84 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/1203

Abstract: At least one method, apparatus and system disclosed involves providing a design for manufacturing a semiconductor device. A first functional cell having a first width is placed on a circuit layout. A determination is made as to whether at least one transistor of the first functional cell is to be forward biased or reversed biased. A second functional cell having a second width is placed adjacent to the first functional cell on the circuit layout for providing a first biasing well within the total width of the first and second functional cells in response to determining that the at least one transistor is to be forward biased or reversed biased.

Abstract translation: 所公开的至少一种方法，装置和系统涉及提供用于制造半导体器件的设计。 具有第一宽度的第一功能单元被放置在电路布局上。 确定第一功能单元的至少一个晶体管是正向偏置还是反向偏置。 具有第二宽度的第二功能单元被布置在电路布局上与第一功能单元相邻，以响应于确定至少一个晶体管将在第一和第二功能单元的总宽度内提供第一偏置阱 正向偏向或反向偏向。

公开(公告)号：US09536035B2

公开(公告)日：2017-01-03

申请号：US14809698

申请日：2015-07-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lei Yuan ,  Juhan Kim ,  Jongwook Kye ,  Mahbub Rashed

IPC: H01L23/52 ,  G06F17/50 ,  H01L23/522 ,  H01L27/02 ,  H01L27/118

CPC classification number: G06F17/5077 ,  H01L23/5226 ,  H01L27/0207 ,  H01L27/11807 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments described herein provide approaches for improved circuit routing using a wide-edge pin. Specifically, provided is an integrated circuit (IC) device comprising a standard cell having a first metal layer (M1) pin coupled to a second metal layer (M2) wire at a via. The M1 pin has a width greater than a width of the via sufficient to satisfy an enclosure rule for the via, while the M1 pin extends vertically past the via a distance substantially equal to or greater than zero. This layout increases the number of available pin access points within the standard cell and thus improves routing efficiency and chip size.

Abstract translation: 本文描述的实施例提供了使用宽边缘引脚改进电路布线的方法。 具体地，提供了一种集成电路（IC）装置，其包括具有在通孔处耦合到第二金属层（M2）线的第一金属层（M1）引脚的标准单元。 M1引脚的宽度大于通孔的宽度，足以满足通孔的外壳规则，而M1引脚垂直延伸超过基本上等于或大于零的距离。 该布局增加了标准单元内可用引脚接入点的数量，从而提高了布线效率和芯片尺寸。

公开(公告)号：US20160268204A1

公开(公告)日：2016-09-15

申请号：US15164114

申请日：2016-05-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Mahbub Rashed ,  Irene Y. Lin ,  Steven Soss ,  Jeff Kim ,  Chinh Nguyen ,  Marc Tarabbia ,  Scott Johnson ,  Subramani Kengeri ,  Suresh Venkatesan

IPC: H01L23/535 ,  H01L29/08 ,  H01L27/092 ,  H01L23/532 ,  H01L21/8238 ,  H01L21/285

CPC classification number: H01L23/535 ,  H01L21/28518 ,  H01L21/76895 ,  H01L21/823418 ,  H01L21/823475 ,  H01L21/823814 ,  H01L21/823871 ,  H01L23/53238 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/11807 ,  H01L29/0847 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device is provided for implementing at least one logic element. The semiconductor device includes a semiconductor substrate with a first transistor and a second transistor formed on the semiconductor substrate. Each of the transistors comprises a source, a drain, and a gate. A trench silicide layer electrically connects one of the source or the drain of the first transistor to one of the source or the drain of the second transistor.

公开(公告)号：US09105643B2

公开(公告)日：2015-08-11

申请号：US14337596

申请日：2014-07-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Juhan Kim ,  Mahbub Rashed

IPC: H01L29/40 ,  H01L23/48 ,  H01L21/337 ,  H01L21/205 ,  H01L23/538 ,  H01L27/02 ,  H01L27/11

CPC classification number: H01L23/5386 ,  H01L27/0207 ,  H01L27/11 ,  H01L27/1104 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An approach for providing SRAM bit cells with double patterned metal layer structures is disclosed. Embodiments include: providing, via a first patterning process, a word line structure, a ground line structure, a power line structure, or a combination thereof; and providing, via a second patterning process, a bit line structure proximate the word line structure, the ground line structure, the power line structure, or a combination thereof. Embodiments include: providing a first landing pad as the word line structure, and a second landing pad as the ground line structure; and providing the first landing pad to have a first tip edge and a first side edge, and the second landing pad to have a second tip edge and a second side edge, wherein the first side edge faces the second side edge.

Abstract translation: 公开了一种提供具有双图案化金属层结构的SRAM位单元的方法。 实施例包括：经由第一图案化工艺提供字线结构，接地线结构，电力线结构或其组合; 以及经由第二图案化处理提供靠近所述字线结构，所述接地线结构，所述电力线结构或其组合的位线结构。 实施例包括：提供作为字线结构的第一着陆焊盘和作为接地线结构的第二着陆焊盘; 以及提供所述第一着陆垫具有第一末端边缘和第一侧边缘，并且所述第二着陆垫具有第二末端边缘和第二侧边缘，其中所述第一侧边缘面向所述第二侧边缘。

公开(公告)号：US08904324B2

公开(公告)日：2014-12-02

申请号：US13836057

申请日：2013-03-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Navneet Jain ,  Paul D. Mesa ,  Qinglei Wang ,  Qi Xiang ,  Mahbub Rashed

IPC: G06F17/50

CPC classification number: G06F17/5068 ,  G06F17/505 ,  H01L29/66795

Abstract: A parameterized cell for planar and finFET designs is provided. A parameterized cell (Pcell) describing a planar design is integrated with fin-based design criteria, including fin pitch. For material regions in a planar design that have a corresponding region in a fin design, a quantized value based on the fin pitch is computed. The material can include regions such as active area silicon, contact regions, and local interconnect regions.

Abstract translation: 提供了用于平面和finFET设计的参数化单元。 描述平面设计的参数化单元（Pcell）集成了基于翅片的设计标准，包括翅片间距。 对于在翅片设计中具有对应区域的平面设计中的材料区域，计算基于翅片间距的量化值。 该材料可以包括诸如有源区硅，接触区域和局部互连区域的区域。

公开(公告)号：US20140327153A1

公开(公告)日：2014-11-06

申请号：US13886423

申请日：2013-05-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Lei Yuan ,  Mahbub Rashed ,  Irene Yuh-Ling Lin ,  Jongwook Kye

IPC: G06F17/50 ,  H01L23/522

CPC classification number: G06F17/5077 ,  H01L23/5221 ,  H01L23/5286 ,  H01L27/0207 ,  H01L27/11807 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments described herein provide approaches for improving a standard cell connection for circuit routing. Specifically, provided is an IC device having a plurality of cells, a first metal layer (M1) pin coupled to a contact bar extending from a first cell of the plurality of cells, and a second metal layer (M2) wire coupled to the contact bar, wherein the contact bar extends across at least one power rail. By extending the contact bar into an open area between the plurality of cells to couple the M1 pin and the M2 wire, routing efficiency and chip scaling are improved.

Abstract translation: 本文描述的实施例提供了用于改进电路布线的标准单元连接的方法。 具体地，提供有具有多个单元的IC器件，耦合到从多个单元的第一单元延伸的接触棒的第一金属层（M1）引脚和耦合到该触点的第二金属层（M2）线 杆，其中接触杆延伸穿过至少一个电源轨。 通过将接触杆延伸到多个单电池之间的开放区域中以耦合M1引脚和M2线，提高了布线效率和芯片缩放。

公开(公告)号：US08881083B1

公开(公告)日：2014-11-04

申请号：US13874803

申请日：2013-05-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yunfei Deng ,  Lei Yuan ,  Hidekazu Yoshida ,  Juhan Kim ,  Mahbub Rashed ,  Jongwook Kye

IPC: G06F17/50 ,  H01L23/48

CPC classification number: G06F17/5077 ,  G06F17/5072 ,  H01L27/0207 ,  H01L27/11807 ,  H01L2027/11831 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A design methodology for routing for an integrated circuit is disclosed. The method includes placement of cells having double diffusion breaks, which create an extended intercell region. Metal layer prohibit zones are defined to prohibit any M1 structures in the prohibit zones. Metal layer allow zones are placed adjacent to outer metal lines, and jogs are formed in the metal layer allow zones. Vias and viabars may then be applied on the jogs.

Abstract translation: 公开了用于集成电路布线的设计方法。 该方法包括放置具有双扩散断裂的电池，这产生扩展的电池间​​区域。 金属层禁止区被定义为禁止禁区内的任何M1结构。 金属层允许区域邻近外部金属线放置，并且在金属层中形成点动允许区域。 然后将通风口和viabars应用于慢跑。

公开(公告)号：US20140282323A1

公开(公告)日：2014-09-18

申请号：US13836057

申请日：2013-03-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Navneet Jain ,  Paul D. Mesa ,  Qinglei Wang ,  Qi Xiang ,  Mahbub Rashed

IPC: G06F17/50

CPC classification number: G06F17/5068 ,  G06F17/505 ,  H01L29/66795

Abstract: A parameterized cell for planar and finFET designs is provided. A parameterized cell (Pcell) describing a planar design is integrated with fin-based design criteria, including fin pitch. For material regions in a planar design that have a corresponding region in a fin design, a quantized value based on the fin pitch is computed. The material can include regions such as active area silicon, contact regions, and local interconnect regions.

Abstract translation: 提供了用于平面和finFET设计的参数化单元。 描述平面设计的参数化单元（Pcell）集成了基于翅片的设计标准，包括翅片间距。 对于在翅片设计中具有对应区域的平面设计中的材料区域，计算基于翅片间距的量化值。 该材料可以包括诸如有源区硅，接触区域和局部互连区域的区域。

公开(公告)号：US10833018B2

公开(公告)日：2020-11-10

申请号：US16502521

申请日：2019-07-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Mahbub Rashed ,  Irene Y. Lin ,  Steven Soss ,  Jeff Kim ,  Chinh Nguyen ,  Marc Tarabbia ,  Scott Johnson ,  Subramani Kengeri ,  Suresh Venkatesan

IPC: H01L23/535 ,  H01L21/8234 ,  H01L27/02 ,  H01L21/768 ,  H01L21/285 ,  H01L21/8238 ,  H01L23/532 ,  H01L27/092 ,  H01L29/08 ,  H01L27/118

Abstract: A semiconductor device includes a substrate with first and second transistors disposed thereon and including sources, drains, and gates, wherein the first and second gates extend longitudinally as part of linear strips that are parallel to and spaced apart. The device further includes a first CB layer forming a local interconnect electrically connected to the first gate, a second CB layer forming a local interconnect electrically connected to the second gate, and a CA layer forming a local interconnect extending longitudinally between first and second ends of the CA layer. The first and second CB layers and the CA layer are disposed between a first metal layer and the substrate. The first metal layer is disposed above each source, drain, and gate of the transistors, The CA layer extends parallel to the first and second linear strips and is substantially perpendicular to the first and second CB layers.