公开(公告)号：US20210249518A1

公开(公告)日：2021-08-12

申请号：US16788922

申请日：2020-02-12

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Wei Hong ,  Yanping Shen ,  Domingo A. Ferrer ,  Hong Yu

IPC: H01L29/45 ,  H01L29/417 ,  H01L29/08 ,  H01L27/088 ,  H01L29/165 ,  H01L21/285 ,  H01L29/66

Abstract: Embodiments of the disclosure provide an integrated circuit (IC) structure with a niobium-based silicide layer. An IC structure according to the disclosure includes a transistor on a substrate, the transistor including a gate structure above the substrate and a source/drain (S/D) region on the substrate adjacent the gate structure. A niobium-based silicide layer is on at least an upper surface the S/D region of the transistor, and extends across substantially an entire width of the S/D region. An S/D contact to the S/D region is in contact with the niobium-based silicide layer.

公开(公告)号：US20210217887A1

公开(公告)日：2021-07-15

申请号：US16739299

申请日：2020-01-10

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Jiehui Shu ,  Haiting Wang ,  Hong Yu

IPC: H01L29/78 ,  H01L27/088 ,  H01L21/762 ,  H01L29/66

Abstract: A transistor device that includes a single semiconductor structure having an outer perimeter and a vertical height, wherein the single semiconductor structure is at least partially defined by a trench formed in a semiconductor substrate and a first layer of material positioned on the bottom surface of the trench and around the outer perimeter of the single semiconductor structure. The device also includes a second layer of material positioned on the first layer of material and around the outer perimeter of the single semiconductor structure, a gap between the outer perimeter of the single semiconductor structure and both the first and second layers of material (when considered collectively) and an insulating sidewall spacer positioned in the gap, wherein the insulating sidewall spacer has a vertical height that is less than the vertical height of the single semiconductor structure.

公开(公告)号：US10971583B2

公开(公告)日：2021-04-06

申请号：US16188408

申请日：2018-11-13

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Hong Yu ,  Hui Zang ,  Jiehui Shu

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L27/088 ,  H01L21/033 ,  H01L21/8234 ,  H01L21/764 ,  H01L21/768

Abstract: A gate cut isolation including an air gap and an IC including the same are disclosed. A method of forming the gate cut isolation may include forming an opening in a dummy gate that extends over a plurality of spaced active regions, the opening positioned between and spaced from a pair of active regions. The opening is filled with a fill material, and the dummy gate is removed. A metal gate is formed in a space vacated by the dummy gate on each side of the fill material, and the fill material is removed to form a preliminary gate cut opening. A liner is deposited in the preliminary gate cut opening, creating a gate cut isolation opening, which is then sealed by depositing a sealing layer. The sealing layer closes an upper end of the gate cut isolation opening and forms the gate cut isolation including an air gap.

公开(公告)号：US12261215B2

公开(公告)日：2025-03-25

申请号：US17649184

申请日：2022-01-27

Applicant: GlobalFoundries U.S. Inc.

Inventor： Hong Yu ,  Haiting Wang ,  Zhenyu Hu

IPC: H01L29/78 ,  H01L21/8234 ,  H01L29/66

Abstract: A structure is provided, the structure may include an active layer arranged over a buried oxide layer, the active layer having a top surface. The top surface of the active layer may have a first portion and a second portion. A barrier stack may be arranged over the first portion of the top surface of the active layer. The barrier stack may include a barrier layer. The second portion of the top surface of the active layer may be adjacent to the barrier stack. A fin may be spaced from the first portion of the top surface of the active layer by the barrier stack, the fin having a first side surface, a second side surface opposite to the first side surface and a top surface. A dielectric layer may be arranged on the first side surface, the second side surface and the top surface of the fin, and the second portion of the top surface of the active layer. A metal layer may be arranged over the dielectric layer.

公开(公告)号：US20250040237A1

公开(公告)日：2025-01-30

申请号：US18358157

申请日：2023-07-25

Applicant: GlobalFoundries U.S. Inc.

Inventor： Vitor A. Vulcano Rossi ,  Anton V. Tokranov ,  Hong Yu ,  David C. Pritchard

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/10 ,  H01L29/66

Abstract: An integrated circuit includes a fin having a height and a width under a gate of a selected fin-type field effect transistor (FinFET) that is less than the height and width along a remainder of the fin including under gates and for source/drain regions of other FinFETs. The IC includes a first FinFET having a first gate over a fin having a first height and a first width under the first gate, and a second FinFET in the fin adjacent to the first FinFET. The second FinFET has a second gate over the fin, and the fin has, under the second gate only, a second height less than the first height and a second width less than the first width. The resulting reduced channel height and width for the second FinFET increases gate control and reduces gate leakage, which is beneficial for ultra-low current leakage (ULL) devices.

公开(公告)号：US20240313054A1

公开(公告)日：2024-09-19

申请号：US18183468

申请日：2023-03-14

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Jianwei PENG ,  Hong Yu

IPC: H01L29/08 ,  H01L21/8238 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/0847 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/41783 ,  H01L29/42364 ,  H01L29/6656 ,  H01L21/31144

Abstract: An apparatus has a first gate structure of a core device on a substrate, a first L-shaped spacer covering a sidewall of the first gate and part of the substrate adjacent to the first gate, a first raised source/drain (S/D) structure on the substrate and spaced apart from the first gate by the first L-shaped spacer, a second gate of an I/O device on the substrate, a second L-shaped spacer covering a sidewall of the second gate and part of the substrate adjacent to the second gate, and a second raised S/D structure spaced apart from the second gate by the second L-shaped spacer. The first and second L-shaped spacers have the same spacer width, and a distance between the first gate structure and a sidewall of the first S/D structure is less than a distance between the second gate structure and a sidewall of the second S/D structure.

公开(公告)号：US12040388B2

公开(公告)日：2024-07-16

申请号：US17525634

申请日：2021-11-12

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Hong Yu ,  Judson R. Holt ,  Alexander Derrickson

IPC: H01L29/735 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165 ,  H01L29/66

CPC classification number: H01L29/735 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/1008 ,  H01L29/165 ,  H01L29/6625

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a lateral bipolar transistor and methods of manufacture. The structure includes: an extrinsic base having at least one sidewall with a gradient concentration of semiconductor material; an emitter on a first side of the extrinsic base; and a collector on a second side of the extrinsic base.

公开(公告)号：US20240172455A1

公开(公告)日：2024-05-23

申请号：US17990800

申请日：2022-11-21

Applicant: GlobalFoundries U.S. Inc.

Inventor： John J. Pekarik ,  Hong Yu ,  Vibhor Jain ,  Alexander Derrickson ,  Venkatesh Gopinath

IPC: H01L47/00 ,  H01L29/66 ,  H01L29/737

CPC classification number: H01L27/2445 ,  H01L29/66242 ,  H01L29/7371 ,  H01L45/1233 ,  H01L45/16

Abstract: Structures that include bipolar junction transistors and methods of forming such structures. The structure comprises a substrate having a top surface, a trench isolation region in the substrate, and a base layer on the top surface of the substrate. The base layer extending across the trench isolation region. A first bipolar junction transistor includes a first collector in the substrate and a first emitter on a first portion of the first base layer. The first portion of the first base layer is positioned between the first collector and the first emitter. A second bipolar junction transistor includes a second collector in the substrate and a second emitter on a second portion of the first base layer. The second portion of the first base layer is positioned between the second collector and the second emitter.

公开(公告)号：US11935927B2

公开(公告)日：2024-03-19

申请号：US17684321

申请日：2022-03-01

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Hong Yu ,  Vibhor Jain

IPC: H01L29/417 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66 ,  H01L29/735 ,  H01L29/737

CPC classification number: H01L29/41708 ,  H01L29/0821 ,  H01L29/1008 ,  H01L29/66242 ,  H01L29/735 ,  H01L29/737 ,  H01L29/0808 ,  H01L29/0817

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a bipolar transistor with a collector contact and methods of manufacture. The structure includes: a lateral bipolar transistor which includes an emitter, a base and a collector; an emitter contact to the emitter; a base contact to the base; and a collector contact to the collector and extending to an underlying substrate underneath the collector.

公开(公告)号：US11843044B2

公开(公告)日：2023-12-12

申请号：US17578687

申请日：2022-01-19

Applicant: GlobalFoundries U.S. Inc.

Inventor： Hong Yu ,  Alexander M. Derrickson ,  Judson R. Holt

IPC: H01L29/735 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L29/735 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/41708 ,  H01L29/6625

Abstract: Embodiments of the disclosure provide a bipolar transistor structure on a semiconductor fin. The semiconductor fin may be on a substrate and may have a first doping type, a length in a first direction, and a width in a second direction perpendicular to the first direction. The semiconductor fin includes a first portion and a second portion adjacent the first portion along the length of the semiconductor fin. The second portion is coupled to a base contact. A dopant concentration of the first portion is less than a dopant concentration of the second portion. An emitter/collector (E/C) material is adjacent the first portion along the width of the semiconductor fin. The E/C material has a second doping type opposite the first doping type. The E/C material is coupled to an E/C contact.