公开(公告)号：US20240170561A1

公开(公告)日：2024-05-23

申请号：US17990931

申请日：2022-11-21

Applicant: GlobalFoundries U.S. Inc.

Inventor： Vibhor Jain ,  Jeffrey Johnson ,  Viorel Ontalus ,  John J. Pekarik

IPC: H01L29/737 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L29/7378 ,  H01L29/0817 ,  H01L29/66242

Abstract: Structures for a heterojunction bipolar transistor and methods of forming a structure for a heterojunction bipolar transistor. The structure comprises an emitter, a collector including a first section, a second section, and a third section positioned in a first direction between the first section and the second section, and an intrinsic base disposed in a second direction between the emitter and the third section of the collector. The structure further comprises a stress layer including a section positioned to overlap with the emitter, the intrinsic base, and the collector. The section of the stress layer is surrounded by a perimeter, and the first and second sections of the collector are each positioned adjacent to the perimeter of the stress layer.

公开(公告)号：US11949004B2

公开(公告)日：2024-04-02

申请号：US17533882

申请日：2021-11-23

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Judson R. Holt ,  Vibhor Jain ,  Alexander M. Derrickson

IPC: H01L29/739 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/7393 ,  H01L29/0649 ,  H01L29/66325

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a lateral bipolar transistor and methods of manufacture. The structure includes: an extrinsic base region; an emitter region on a first side of the extrinsic base region; a collector region on a second side of the extrinsic base region; and a gate structure comprising a gate oxide and a gate control in a same channel region as the extrinsic base region.

公开(公告)号：US11935927B2

公开(公告)日：2024-03-19

申请号：US17684321

申请日：2022-03-01

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Hong Yu ,  Vibhor Jain

IPC: H01L29/417 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66 ,  H01L29/735 ,  H01L29/737

CPC classification number: H01L29/41708 ,  H01L29/0821 ,  H01L29/1008 ,  H01L29/66242 ,  H01L29/735 ,  H01L29/737 ,  H01L29/0808 ,  H01L29/0817

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a bipolar transistor with a collector contact and methods of manufacture. The structure includes: a lateral bipolar transistor which includes an emitter, a base and a collector; an emitter contact to the emitter; a base contact to the base; and a collector contact to the collector and extending to an underlying substrate underneath the collector.

公开(公告)号：US20240072180A1

公开(公告)日：2024-02-29

申请号：US17896711

申请日：2022-08-26

Applicant: GlobalFoundries U.S. Inc.

Inventor： Saloni Chaurasia ,  Jeffrey Johnson ,  Vibhor Jain ,  Crystal R. Kenney ,  Sudesh Saroop ,  Teng-Yin Lin ,  John J. Pekarik

IPC: H01L29/93 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L29/93 ,  H01L29/1095 ,  H01L29/66174

Abstract: Structures for a varactor diode and methods of forming same. The structure comprises a first semiconductor layer including a section on a substrate, a second semiconductor layer on the section of the first semiconductor layer, a third semiconductor layer on the second semiconductor layer, and a doped region in the section of the first semiconductor layer. The section of the first semiconductor layer and the doped region have a first conductivity type, and the second semiconductor layer comprises silicon-germanium having a second conductivity type opposite to the first conductivity type, and the third semiconductor layer has the second conductivity type. The doped region contains a higher concentration of a dopant of the first conductivity type than the section of the first semiconductor layer. The second semiconductor layer abuts the first section of the first semiconductor layer along an interface, and the doped region is positioned adjacent to the interface.

公开(公告)号：US11876123B2

公开(公告)日：2024-01-16

申请号：US17214969

申请日：2021-03-29

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Anthony K. Stamper ,  Vibhor Jain ,  Renata A. Camillo-Castillo

IPC: H01L21/762 ,  H01L29/66 ,  H01L29/08 ,  H01L29/10 ,  H01L29/06 ,  H01L29/737 ,  H01L29/732

CPC classification number: H01L29/66242 ,  H01L21/762 ,  H01L21/76224 ,  H01L29/0603 ,  H01L29/0649 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/66272 ,  H01L29/7371 ,  H01L29/732

Abstract: According to a semiconductor device herein, the device includes a substrate. An active device is formed in the substrate. The active device includes a collector region, a base region formed on the collector region, and an emitter region formed on the base region. An isolation structure is formed in the substrate around the active device. A trench filled with a compressive material is formed in the substrate and positioned laterally adjacent to the emitter region and base region. The trench extends at least partially into the collector region.

公开(公告)号：US11815717B2

公开(公告)日：2023-11-14

申请号：US17525293

申请日：2021-11-12

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Vibhor Jain ,  Nicholas A. Polomoff ,  Yusheng Bian

IPC: G02B6/12 ,  G02B6/122 ,  G02B6/24 ,  H01L23/00

CPC classification number: G02B6/122 ,  G02B6/243 ,  H01L23/573 ,  G02B2006/12061 ,  G02B2006/12126

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a photonic chip security structure and methods of manufacture. The structure includes an optical component and a photonic chip security structure having a vertical wall composed of light absorbing material surrounding the optical component.

公开(公告)号：US11810969B2

公开(公告)日：2023-11-07

申请号：US17509384

申请日：2021-10-25

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Haiting Wang ,  Alexander Derrickson ,  Jagar Singh ,  Vibhor Jain ,  Andreas Knorr ,  Alexander Martin ,  Judson R. Holt ,  Zhenyu Hu

IPC: H01L29/735 ,  H01L29/66 ,  H01L29/737 ,  H01L29/08 ,  H01L29/417

CPC classification number: H01L29/735 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/41708 ,  H01L29/6625 ,  H01L29/737

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a lateral bipolar transistor and methods of manufacture. A structure includes: an intrinsic base comprising semiconductor material in a channel region of a semiconductor substrate; an extrinsic base vertically above the intrinsic base; a raised collector region on the semiconductor substrate and laterally connected to the intrinsic base; and a raised emitter region on the semiconductor substate and laterally connected to the intrinsic base.

公开(公告)号：US20230268401A1

公开(公告)日：2023-08-24

申请号：US17747476

申请日：2022-05-18

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Hong Yu ,  Jianwei Peng ,  Vibhor Jain

IPC: H01L29/417 ,  H01L29/737 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/41708 ,  H01L29/7371 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/1008 ,  H01L29/42304 ,  H01L29/66242

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a bipolar transistor with self-aligned asymmetric spacer and methods of manufacture. The structure includes: a base formed on a semiconductor substrate; an asymmetrical spacer surrounding the base; an emitter on a first side of the base and separated from the base by the asymmetrical spacer; and a collector on a second side of the base and separated from the base by the asymmetrical spacer.

公开(公告)号：US11721719B2

公开(公告)日：2023-08-08

申请号：US17074891

申请日：2020-10-20

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Vibhor Jain ,  Anthony K. Stamper ,  John J. Ellis-Monaghan ,  Steven M. Shank ,  Rajendran Krishnasamy

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/737 ,  H01L21/763 ,  H01L29/165

CPC classification number: H01L29/0642 ,  H01L21/763 ,  H01L29/0826 ,  H01L29/165 ,  H01L29/66242 ,  H01L29/7371

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors (HBTs) with a buried trap rich region and methods of manufacture. The structure includes: a trap rich isolation region embedded within the bulk substrate; and a heterojunction bipolar transistor above the trap rich isolation region, with its sub-collector region separated by the trap rich isolation region by a layer of the bulk substrate.

公开(公告)号：US20230067948A1

公开(公告)日：2023-03-02

申请号：US17540339

申请日：2021-12-02

Applicant: GlobalFoundries U.S. Inc.

Inventor： Vibhor Jain ,  Judson R. Holt

IPC: H01L29/739 ,  H01L29/66

Abstract: Structures for a diode and methods of fabricating a structure for a diode. The structure includes a layer comprised of a semiconductor material. The layer includes a first section, a second section, and a third section laterally positioned between the first section and the second section. The structure includes a first terminal having a raised semiconductor layer on the first section of the layer, a second terminal including a portion on the second section of the layer, and a gate on the third section of the layer.