公开(公告)号：US11569405B2

公开(公告)日：2023-01-31

申请号：US16686973

申请日：2019-11-18

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Steven M. Shank ,  Vibhor Jain ,  Anthony K. Stamper ,  John J. Ellis-Monaghan ,  John J. Pekarik

IPC: H01L31/103 ,  H01L31/18 ,  H01L31/028

Abstract: Structures including a photodetector and methods of fabricating such structures. The photodetector is positioned over the top surface of the substrate. The photodetector includes a portion of a semiconductor layer comprised of a semiconductor alloy, a p-type doped region in the portion of the semiconductor layer, and an n-type doped region in the portion of the semiconductor layer. The p-type doped region and the n-type doped region converge along a p-n junction. The portion of the semiconductor layer has a first side and a second side opposite from the first side. The semiconductor alloy has a composition that is laterally graded from the first side to the second side of the portion of the semiconductor layer.

公开(公告)号：US11282883B2

公开(公告)日：2022-03-22

申请号：US16713423

申请日：2019-12-13

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： John J. Ellis-Monaghan ,  Steven M. Shank ,  Vibhor Jain ,  Anthony K. Stamper ,  John J. Pekarik

IPC: H01L31/113 ,  H01L27/146

Abstract: Structures including a photodiode and methods of fabricating such structures. A trench extends from a top surface of a substrate to a depth into the substrate. The photodiode includes an active layer positioned in the trench. Trench isolation regions, which are located in the substrate, are arranged to surround the trench. A portion of the substrate is positioned in a surrounding relationship about the active layer and between the active layer and the trench isolation regions.

公开(公告)号：US11271079B2

公开(公告)日：2022-03-08

申请号：US16743584

申请日：2020-01-15

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Anthony K. Stamper ,  Steven M. Shank ,  John J. Pekarik ,  Vibhor Jain ,  John J. Ellis-Monaghan

IPC: H01L29/16 ,  H01L21/02 ,  H01L27/12 ,  H01L21/762

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a wafer with crystalline silicon and trap rich polysilicon layer and methods of manufacture. The structure includes: semiconductor-on-insulator (SOI) wafer composed of a lower crystalline semiconductor layer, a polysilicon layer over the lower crystalline semiconductor layer, an upper crystalline semiconductor layer over the polysilicon layer, a buried insulator layer over the upper crystalline semiconductor layer, and a top crystalline semiconductor layer over the buried insulator layer.

公开(公告)号：US11171210B2

公开(公告)日：2021-11-09

申请号：US16804435

申请日：2020-02-28

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： John J. Pekarik ,  Vibhor Jain

IPC: H01L29/10 ,  H01L29/66 ,  H01L29/08 ,  H01L29/737

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a heterojunction bipolar transistor and methods of manufacture. The structure includes: a sub-collector region; a collector region above the sub-collector region; an intrinsic base region composed of intrinsic base material located above the collector region; an emitter located above and separated from the intrinsic base material; and a raised extrinsic base having a stepped configuration and separated from and self-aligned to the emitter.

公开(公告)号：US20210280672A1

公开(公告)日：2021-09-09

申请号：US16807453

申请日：2020-03-03

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Anthony K. Stamper ,  Vibhor Jain ,  John J. Pekarik ,  Steven M. Shank ,  John J. Ellis-Monaghan

IPC: H01L29/06 ,  H01L29/04 ,  H01L29/737 ,  H01L27/102 ,  H01L21/762

Abstract: Structures including electrical isolation and methods of forming a structure including electrical isolation. A semiconductor layer is formed over a semiconductor substrate and shallow trench isolation regions are formed in the semiconductor layer. The semiconductor layer includes single-crystal semiconductor material having an electrical resistivity that is greater than or equal to 1000 ohm-cm. The shallow trench isolation regions are arranged to surround a portion of the semiconductor layer to define an active device region. A polycrystalline layer is positioned in the semiconductor layer and extends laterally beneath the active device region and the shallow trench isolation regions that surround the active device region.

公开(公告)号：US20210183918A1

公开(公告)日：2021-06-17

申请号：US16713423

申请日：2019-12-13

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： John J. Ellis-Monaghan ,  Steven M. Shank ,  Vibhor Jain ,  Anthony K. Stamper ,  John J. Pekarik

IPC: H01L27/146

Abstract: Structures including a photodiode and methods of fabricating such structures. A trench extends from a top surface of a substrate to a depth into the substrate. The photodiode includes an active layer positioned in the trench. Trench isolation regions, which are located in the substrate, are arranged to surround the trench. A portion of the substrate is positioned in a surrounding relationship about the active layer and between the active layer and the trench isolation regions.

公开(公告)号：US20240170560A1

公开(公告)日：2024-05-23

申请号：US17990898

申请日：2022-11-21

Applicant: GlobalFoundries U.S. Inc.

Inventor： Alexander Derrickson ,  Venkatesh Gopinath ,  John J. Pekarik ,  Hong Yu ,  Vibhor Jain ,  David Pritchard

IPC: H01L29/735 ,  H01L27/06 ,  H01L29/66 ,  H01L29/732

CPC classification number: H01L29/735 ,  H01L27/0623 ,  H01L29/66871 ,  H01L29/732

Abstract: Structures that include bipolar junction transistors and methods of forming such structures. The structure comprises a semiconductor layer, a substrate, and a dielectric layer disposed between the semiconductor layer and the substrate. The structure further comprises a first bipolar junction transistor including a first collector in the substrate, a first emitter, and a first base layer. The first base layer extends through the dielectric layer from the first emitter to the first collector. The structure further comprises a second bipolar junction transistor including a second collector in the substrate, a second emitter, and a second base layer. The second base layer extends through the dielectric layer from the second emitter to the second collector. The second base layer is connected to the first base layer by a section of the semiconductor layer to define a base line.

公开(公告)号：US11695064B2

公开(公告)日：2023-07-04

申请号：US17176251

申请日：2021-02-16

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Vibhor Jain ,  Judson R. Holt ,  Tayel Nesheiwat ,  John J. Pekarik ,  Christopher Durcan

IPC: H01L29/732 ,  H01L29/66 ,  H01L29/08 ,  H01L29/06

CPC classification number: H01L29/732 ,  H01L29/0649 ,  H01L29/0804 ,  H01L29/66272

Abstract: Device structures and fabrication methods for a bipolar junction transistor. The device structure includes a substrate and a trench isolation region in the substrate. The trench isolation region surrounds an active region of the substrate. The device structure further includes a collector in the active region of the substrate, a base layer having a first section positioned on the active region and a second section oriented at an angle relative to the first section, an emitter positioned on the first section of the base layer, and an extrinsic base layer positioned over the trench isolation region and adjacent to the emitter. The second section of the base layer is laterally positioned between the extrinsic base layer and the emitter.

公开(公告)号：US20230061482A1

公开(公告)日：2023-03-02

申请号：US17455290

申请日：2021-11-17

Applicant: GlobalFoundries U.S. Inc.

Inventor： Hong Yu ,  Jagar Singh ,  Zhenyu Hu ,  John J. Pekarik

IPC: H01L29/10 ,  H01L29/417 ,  H01L29/423 ,  H01L29/735 ,  H01L29/737 ,  H01L29/66 ,  H01L29/40

Abstract: The disclosure provides a lateral bipolar transistor structure with a base layer over a semiconductor buffer, and related methods. A lateral bipolar transistor structure may include an emitter/collector (E/C) layer over an insulator. The E/C layer has a first doping type. A semiconductor buffer is adjacent the insulator. A base layer is on the semiconductor buffer and adjacent the E/C layer, the base layer including a lower surface below the E/C layer and an upper surface above the E/C layer. The base layer has a second doping type opposite the first doping type.

公开(公告)号：US20230057695A1

公开(公告)日：2023-02-23

申请号：US17509327

申请日：2021-10-25

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Vibhor Jain ,  Alvin J. Joseph ,  Alexander Derrickson ,  Judson R. Holt ,  John J. Pekarik

IPC: H01L29/08 ,  H01L29/735 ,  H01L29/417 ,  H01L29/66

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to lateral bipolar transistors and methods of manufacture. The structure includes: an extrinsic base comprising semiconductor material; an intrinsic base comprising semiconductor material which is located below the extrinsic base; a polysilicon emitter on a first side of the extrinsic base; a raised collector on a second side of the extrinsic base; and sidewall spacers on the extrinsic base which separate the extrinsic base from the polysilicon emitter and the raised collector.