公开(公告)号：US6065115A

公开(公告)日：2000-05-16

申请号：US58460

申请日：1998-04-10

申请人： Harshvardhan P. Sharangpani ,  Gary N. Hammond ,  Hans J. Mulder ,  Judge K. Arora

发明人： Harshvardhan P. Sharangpani ,  Gary N. Hammond ,  Hans J. Mulder ,  Judge K. Arora

IPC分类号： G06F9/38 ,  G06F15/60

CPC分类号： G06F9/3804 ,  G06F9/3842 ,  G06F9/3844 ,  G06F9/3851 ,  G06F9/3863

摘要： A microprocessor for efficient processing of instructions in a program flow including a conditional program flow control instruction, such as a branch instruction. The conditional program flow control instruction targets a first code section to be processed if the condition is resolved to be met, and a second code section to be processed if the condition is resolved to be not met. A fetch unit fetches instructions to be processed and branch prediction logic coupled to the fetch unit predicts the resolution of the condition. The branch prediction logic of the invention also determines whether resolution of the condition is unlikely to be predicted accurately. Stream management logic responsive to the branch prediction logic directs speculative processing of instructions from both the first and second code sections prior to resolution of the condition if resolution of the condition is unlikely to be predicted accurately. Results of properly executed instructions are then committed to architectural state in program order. In this manner, the invention reduces the performance penalty related to mispredictions.

摘要翻译： 一种用于在程序流中有效处理指令的微处理器，包括诸如分支指令之类的条件程序流程控制指令。 条件程序流程控制指令如果条件被解析为满足则针对要处理的第一代码段，以及如果条件被解析为不满足则要处理的第二代码段。 提取单元获取要处理的指令，并且耦合到提取单元的分支预测逻辑预测条件的分辨率。 本发明的分支预测逻辑还确定不可能准确地预测条件的分辨率。 响应于分支预测逻辑的流管理逻辑在解决条件之前指导来自第一和第二代码部分的指令的推测性处理，如果条件的分辨率不太可能被准确地预测。 然后，正确执行的指令的结果将以程序顺序提交到架构状态。 以这种方式，本发明降低了与错误预测相关的性能损失。

公开(公告)号：US6055652A

公开(公告)日：2000-04-25

申请号：US314439

申请日：1999-05-19

申请人： Nazar A. Zaidi ,  Kenneth D. Shoemaker ,  Gary N. Hammond

发明人： Nazar A. Zaidi ,  Kenneth D. Shoemaker ,  Gary N. Hammond

IPC分类号： G06F12/14 ,  G06F11/16

CPC分类号： G06F12/1441

摘要： A new method and apparatus are used to check for segment limit violations during memory access. When a segment descriptor is retrieved during the initialization of a segment, the segment limit from the segment descriptor is used to create five limits. The five limits are the last possible address within the segment for each size of memory access. During a subsequent memory access, the limit corresponding to the segment being accessed and the length of memory access is selected. The selected limit is compared against the address of the memory access to determine if a limit violation has occurred. If a limit violation has occurred, a flag is set that, when read, will cause an exception.

公开(公告)号：US5895489A

公开(公告)日：1999-04-20

申请号：US777608

申请日：1991-10-16

申请人： Gary N. Hammond ,  Pradeep Dubey ,  Mustafiz R. Choudhury

发明人： Gary N. Hammond ,  Pradeep Dubey ,  Mustafiz R. Choudhury

IPC分类号： G06F12/08 ,  G06F12/10 ,  G06F12/12

CPC分类号： G06F12/128 ,  G06F12/0815 ,  G06F12/0891 ,  G06F12/1027 ,  G06F2212/682

摘要： A memory management system for a computer, where cache coherency between a descriptor cache and data cache is preserved through an inclusion bit mechanism. In one embodiment, an inclusion bit is set for a descriptor cached in a data cache corresponding to a descriptor cached in a descriptor cache such that the association between the descriptors is indicated. Whenever a descriptor in the data cache with a set inclusion bit is altered, the entire descriptor cache is flushed by virtue of the set inclusion bit. Furthermore, in the same embodiment, a valid bit is set for a descriptor in the data cache which is cached from the descriptor table. Whenever a descriptor in the descriptor table, which has a valid bit set in the data cache, is modified, the valid bit is reset. And if the same descriptor with its valid bit reset has a set inclusion bit, then the entire descriptor cache is flushed. As a result, the cache coherency among descriptor cache, data cache and descriptor table is preserved in this improved memory management system.

摘要翻译： 用于计算机的存储器管理系统，其中描述符缓存和数据高速缓存之间的高速缓存一致性通过包含位机制来保留。 在一个实施例中，为对应于缓存在描述符高速缓存中的描述符的数据高速缓存中的缓存的描述符设置包含位，使得指示描述符之间的关联。 每当具有集合包含位​​的数据高速缓存中的描述符被改变时，整个描述符高速缓存由于设置的包含位而被刷新。 此外，在同一实施例中，对从描述符表缓存的数据高速缓冲存储器中的描述符设置有效位。 每当在数据高速缓冲存储器中设置有效位的描述符表中的描述符被修改时，有效位被复位。 并且如果具有其有效位复位的相同描述符具有集合包含位​​，则整个描述符高速缓存被刷新。 结果，在该改进的存储器管理系统中保留了描述符缓存，数据高速缓存和描述符表之间的高速缓存一致性。

公开(公告)号：US5832260A

公开(公告)日：1998-11-03

申请号：US581031

申请日：1995-12-29

申请人： Judge K. Arora ,  Gary N. Hammond ,  Harshvardhan P. Sharangpani

发明人： Judge K. Arora ,  Gary N. Hammond ,  Harshvardhan P. Sharangpani

IPC分类号： G06F9/32 ,  G06F9/38 ,  G06F9/40

CPC分类号： G06F9/30058 ,  G06F9/30072 ,  G06F9/3842 ,  G06F9/3844 ,  G06F9/3846

摘要： A processor microarchitecture for efficient processing of instructions in a program including a program flow control instruction. The program flow control instruction specifies a target instruction and includes one or more candidate instructions between the target instruction and the program flow control instruction. A fetch unit fetches instructions in the program from the memory. Control logic stores one or more candidate instructions in the buffer prior to resolution of the conditional program flow control instruction in response to the fetch unit fetching a program flow control instruction specifying a target instruction within a predetermined number of instructions from the conditional program flow control instruction. In another embodiment, the candidate instructions are stored only if the conditional branch instruction is considered to be difficult to predict. The execution unit of the invention executes the candidate instructions if the conditional program flow control instruction is resolved to be not taken and ignores the candidate instructions, through no-ops in one embodiment, if the conditional program flow control instruction is resolved to be taken, thus avoiding a misprediction penalty.

摘要翻译： 一种用于在包括程序流控制指令的程序中有效处理指令的处理器微体系结构。 程序流控制指令指定目标指令，并且包括目标指令和程序流控制指令之间的一个或多个候选指令。 提取单元从存储器中获取程序中的指令。 控制逻辑在解决条件程序流程控制指令之前，将缓冲器中的一个或多个候选指令存储在响应于取出单元从条件程序流控制指令获取指定预定数目的指令内的目标指令的程序流控制指令 。 在另一个实施例中，仅当条件分支指令被认为难以预测时才存储候选指令。 如果条件程序流程控制指令被解决为不被采用，则本发明的执行单元通过无操作在一个实施例中忽略候选指令，如果条件程序流控制指令被解决为采用，则执行候选指令， 从而避免误判。

公开(公告)号：US5659679A

公开(公告)日：1997-08-19

申请号：US454087

申请日：1995-05-30

申请人： Donald Alpert ,  Gary N. Hammond

发明人： Donald Alpert ,  Gary N. Hammond

IPC分类号： G06F11/36 ,  G06F11/34

CPC分类号： G06F11/3648 ,  G06F11/3636

摘要： According to one aspect of the invention, an apparatus for providing the source address of an instruction which causes a branch to be taken (e.g., instructs the processor to transfer the flow of execution) is described. In one embodiment, a processor includes a circuit coupled to a source address storage area. In response to the processor executing an instruction which instructs the processor to transfer the flow of execution to another instruction, the circuit stores in the source address storage area the address of the instruction which is causing the transfer in flow of execution.According to another aspect of the invention, a method for profiling is provided. According to this method, a starting address for execution is stored. Then for the instruction currently being executed, it is determined if that instruction will cause a branch from a source address to a destination address. If it was determined a branch will be taken, then the source address of the branch is stored in a source address storage area, the destination address of the branch is stored in another storage area, and a handler is executed. The handler stores indications indicating the instructions identified by the addresses within the address range defined by the starting address and the source address have been executed.

摘要翻译： 根据本发明的一个方面，描述了一种用于提供引起分支的指令的源地址（例如，指示处理器传送执行流程）的装置。 在一个实施例中，处理器包括耦合到源地址存储区域的电路。 响应于处理器执行指示处理器将执行流程传送到另一指令的指令，电路在源地址存储区域中存储正在导致执行流程的指令的地址。 根据本发明的另一方面，提供了一种用于轮廓的方法。 根据该方法，存储执行的起始地址。 然后，对于当前正在执行的指令，确定该指令是否会导致从源地址到目标地址的分支。 如果确定将分支，则将分支的源地址存储在源地址存储区域中，将分支的目的地址存储在另一个存储区域中，并执行处理程序。 处理器存储指示由起始地址和源地址定义的地址范围内的地址所标识的指令已被执行的指示。

公开(公告)号：US5638525A

公开(公告)日：1997-06-10

申请号：US386931

申请日：1995-02-10

申请人： Gary N. Hammond ,  Kevin C. Kahn ,  Donald B. Alpert

发明人： Gary N. Hammond ,  Kevin C. Kahn ,  Donald B. Alpert

IPC分类号： G06F9/30 ,  G06F9/318 ,  G06F9/38 ,  G06F9/455

CPC分类号： G06F9/3822 ,  G06F9/30043 ,  G06F9/30054 ,  G06F9/30076 ,  G06F9/30123 ,  G06F9/30174 ,  G06F9/30189 ,  G06F9/30196 ,  G06F9/45533

摘要： A data processor is described. The data processor is capable of decoding and executing the first instruction of a first instruction set and the second instruction of a second instruction set wherein the first instruction and the second instruction originate from a single computer program. Alternatively, the data processor can also execute a first instruction of a first instruction set in a first instruction set mode, receive a first interruption indication in the first instruction set mode, service the first interruption indication in a second instruction set mode, return to the first instruction set mode, receive a second interruption indication in the first instruction set mode, and service the second interruption indication in the first instruction set mode.

摘要翻译： 描述数据处理器。 数据处理器能够解码和执行第一指令集的第一指令和第二指令集的第二指令，其中第一指令和第二指令源于单个计算机程序。 或者，数据处理器还可以以第一指令集模式执行第一指令集的第一指令，以第一指令集模式接收第一中断指示，以第二指令集模式服务第一中断指示，返回到 第一指令集模式，以第一指令集模式接收第二中断指示，并在第一指令集模式下服务第二中断指示。

公开(公告)号：US4920536A

公开(公告)日：1990-04-24

申请号：US258202

申请日：1988-10-14

申请人： Gary N. Hammond ,  Michael D. Taylor ,  Nongnuch Taylor

发明人： Gary N. Hammond ,  Michael D. Taylor ,  Nongnuch Taylor

IPC分类号： G06F11/00 ,  G06F11/10 ,  G06F12/08

CPC分类号： G06F11/0751 ,  G06F12/0804 ,  G06F11/10 ,  G06F11/1064

摘要： In a data processing system in which a processor has a cache receiving data staged from at least two main memories. Performance is enhanced by providing an indicator identifying the main memory from which data is staged. When data in the cache is destaged, the indicator is used to direct the destaged data to the proper main memory. If an error occur in the indicator, the data will be destaged to each main memory where a check is made on the address of the data to determine whether the main memory is the source of the destaged data. The data is stored in a main memory only if the memory is the source thereof.

摘要翻译： 在处理器具有从至少两个主存储器分级的高速缓存接收数据的数据处理系统中。 通过提供标识数据分段的主存储器的指标来增强性能。 当缓存中的数据发生故障时，该指示器用于将已分配的数据引导到正确的主存储器。 如果指示符中出现错误，则数据将转移到每个主存储器，在该地址上进行检查，以确定主存储器是否是去往数据的源。 仅当内存是其来源时，才将数据存储在主存储器中。