公开(公告)号：US20120139080A1

公开(公告)日：2012-06-07

申请号：US12959824

申请日：2010-12-03

申请人： Geng Wang ,  Roger A. Booth, JR. ,  Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi

发明人： Geng Wang ,  Roger A. Booth, JR. ,  Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi

IPC分类号： H01L21/70 ,  H01L21/20

CPC分类号： H01L28/40 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/743 ,  H01L21/76224 ,  H01L21/76229 ,  H01L21/84 ,  H01L27/1087 ,  H01L27/1203 ,  H01L28/91 ,  H01L29/0649 ,  H01L29/66181

摘要： A semiconductor structure is provided that includes a material stack including an epitaxially grown semiconductor layer on a base semiconductor layer, a dielectric layer on the epitaxially grown semiconductor layer, and an upper semiconductor layer present on the dielectric layer. A capacitor is present extending from the upper semiconductor layer through the dielectric layer into contact with the epitaxially grown semiconductor layer. The capacitor includes a node dielectric present on the sidewalls of the trench and an upper electrode filling at least a portion of the trench. A substrate contact is present in a contact trench extending from the upper semiconductor layer through the dielectric layer and the epitaxially semiconductor layer to a doped region of the base semiconductor layer. A substrate contact is also provided that contacts the base semiconductor layer through the sidewall of a trench. Methods for forming the above-described structures are also provided.

摘要翻译： 提供一种半导体结构，其包括在基底半导体层上包含外延生长的半导体层的材料堆叠，外延生长的半导体层上的电介质层和存在于电介质层上的上半导体层。 存在从上半导体层通过电介质层延伸到与外延生长的半导体层接触的电容器。 电容器包括存在于沟槽的侧壁上的节点电介质和填充沟槽的至少一部分的上电极。 在从上半导体层通过电介质层和外延半导体层延伸到基底半导体层的掺杂区域的接触沟槽中存在衬底接触。 还提供了通过沟槽的侧壁接触基底半导体层的衬底接触。 还提供了形成上述结构的方法。

公开(公告)号：US20120122315A1

公开(公告)日：2012-05-17

申请号：US12943956

申请日：2010-11-11

申请人： ROGER A. BOOTH, JR. ,  Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

发明人： ROGER A. BOOTH, JR. ,  Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

IPC分类号： H01L21/302 ,  G06F17/50 ,  H01L21/3205

CPC分类号： H01L21/31056 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/32139

摘要： A method includes forming patterned lines on a substrate having a predetermined pitch. The method further includes forming spacer sidewalls on sidewalls of the patterned lines. The method further includes forming material in a space between the spacer sidewalls of adjacent patterned lines. The method further includes forming another patterned line from the material by protecting the material in the space between the spacer sidewalls of adjacent patterned lines while removing the spacer sidewalls. The method further includes transferring a pattern of the patterned lines and the another patterned line to the substrate.

摘要翻译： 一种方法包括在具有预定间距的基底上形成图案线。 该方法还包括在图案化线的侧壁上形成间隔壁。 该方法还包括在相邻图案线的间隔壁侧壁之间的空间中形成材料。 该方法还包括通过在相邻图案化线的间隔壁侧壁之间的空间中保护材料同时去除间隔壁侧壁而从该材料形成另一图案化线。 该方法还包括将图案化线和另一图案化线的图案转移到衬底。

公开(公告)号：US08936996B2

公开(公告)日：2015-01-20

申请号：US12958429

申请日：2010-12-02

申请人： Ravi M. Todi ,  Joseph Ervin ,  Chengwen Pei ,  Geng Wang

发明人： Ravi M. Todi ,  Joseph Ervin ,  Chengwen Pei ,  Geng Wang

IPC分类号： H01L21/76 ,  H01L29/02 ,  H01L21/762

CPC分类号： H01L29/02 ,  H01L21/76254

摘要： A semiconductor structure is provided that includes a semiconductor oxide layer having features. The semiconductor oxide layer having the features is located between an active semiconductor layer and a handle substrate. The semiconductor structure includes a planarized top surface of the active semiconductor layer such that the semiconductor oxide layer is beneath the planarized top surface. The features within the semiconductor oxide layer are mated with a surface of the active semiconductor layer.

摘要翻译： 提供了包括具有特征的半导体氧化物层的半导体结构。 具有特征的半导体氧化物层位于有源半导体层和手柄基板之间。 半导体结构包括有源半导体层的平坦化顶表面，使得半导体氧化物层位于平坦化的顶表面之下。 半导体氧化物层内的特征与有源半导体层的表面配合。

公开(公告)号：US20120139085A1

公开(公告)日：2012-06-07

申请号：US12958429

申请日：2010-12-02

申请人： Ravi M. Todi ,  Joseph Ervin ,  Chengwen Pei ,  Geng Wang

发明人： Ravi M. Todi ,  Joseph Ervin ,  Chengwen Pei ,  Geng Wang

IPC分类号： H01L29/38 ,  H01L21/3213

CPC分类号： H01L29/02 ,  H01L21/76254

摘要： A semiconductor structure is provided that includes a semiconductor oxide layer having features. The semiconductor oxide layer having the features is located between an active semiconductor layer and a handle substrate. The semiconductor structure includes a planarized top surface of the active semiconductor layer such that the semiconductor oxide layer is beneath the planarized top surface. The features within the semiconductor oxide layer are mated with a surface of the active semiconductor layer.

摘要翻译： 提供了包括具有特征的半导体氧化物层的半导体结构。 具有特征的半导体氧化物层位于有源半导体层和手柄基板之间。 半导体结构包括有源半导体层的平坦化顶表面，使得半导体氧化物层位于平坦化的顶表面之下。 半导体氧化物层内的特征与有源半导体层的表面配合。

公开(公告)号：US09059248B2

公开(公告)日：2015-06-16

申请号：US13369382

申请日：2012-02-09

申请人： Joseph Ervin ,  Kangguo Cheng ,  Chengwen Pei ,  Geng Wang

发明人： Joseph Ervin ,  Kangguo Cheng ,  Chengwen Pei ,  Geng Wang

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L21/762 ,  H01L21/84 ,  H01L27/12

CPC分类号： H01L21/76283 ,  H01L21/84 ,  H01L27/1203

摘要： A method of forming a semiconductor device including forming well trenches on opposing sides of a gate structure by removing portions of a semiconductor on insulator (SOI) layer of an semiconductor on insulator (SOI) substrate, wherein the base of the well trenches is provided by a surface of a buried dielectric layer of the SOI substrate and sidewalls of the well trenches are provided by a remaining portion of the SOI layer. Forming a dielectric fill material at the base of the well trenches, wherein the dielectric fill material is in contact with the sidewalls of the well trenches and at least a portion of the surface of the buried dielectric layer that provides the base of the well trenches. Forming a source region and a drain region in the well trenches with an in-situ doped epitaxial semiconductor material.

摘要翻译： 一种形成半导体器件的方法，包括通过去除绝缘体上半导体（SOI）衬底上的半导体绝缘体（SOI）层的部分，在栅极结构的相对侧上形成阱沟，其中阱沟的基极由 SOI衬底的掩埋介电层的表面和阱沟的侧壁由SOI层的剩余部分提供。 在阱沟的底部形成介电填充材料，其中介质填充材料与阱沟槽的侧壁和提供阱沟的基底的掩埋介电层的表面的至少一部分接触。 在原位掺杂的外延半导体材料的阱沟中形成源极区和漏极区。

公开(公告)号：US08492811B2

公开(公告)日：2013-07-23

申请号：US12886224

申请日：2010-09-20

申请人： Roger A. Booth, Jr. ,  Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Geng Wang

发明人： Roger A. Booth, Jr. ,  Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Geng Wang

IPC分类号： H01L27/108

CPC分类号： H01L27/10876 ,  H01L21/84 ,  H01L27/10873 ,  H01L27/10894 ,  H01L27/1203 ,  H01L29/66181 ,  H01L29/945

摘要： After forming a planarization dielectric layer in a replacement gate integration scheme, disposable gate structures are removed and a stack of a gate dielectric layer and a gate electrode layer is formed within recessed gate regions. Each gate electrode structure is then recessed below a topmost surface of the gate dielectric layer. A dielectric metal oxide portion is formed above each gate electrode by planarization. The dielectric metal oxide portions and gate spacers are employed as a self-aligning etch mask in combination with a patterned photoresist to expose and metalize semiconductor surfaces of a source region and an inner electrode in each embedded memory cell structure. The metalized semiconductor portions form metal semiconductor alloy straps that provide a conductive path between the inner electrode of a capacitor and the source of an access transistor.

摘要翻译： 在替代栅极集成方案中形成平坦化介电层之后，去除一次性栅极结构，并且在凹入的栅极区内形成栅极电介质层和栅极电极层的堆叠。 然后，每个栅极电极结构凹陷在栅极电介质层的最上表面之下。 通过平面化形成在每个栅电极上方的介电金属氧化物部分。 电介质金属氧化物部分和栅极间隔物用作自对准蚀刻掩模与图案化的光致抗蚀剂组合以在每个嵌入的存储器单元结构中暴露和金属化源极区域和内部电极的半导体表面。 金属化半导体部分形成金属半导体合金带，其在电容器的内部电极和存取晶体管的源之间提供导电路径。

公开(公告)号：US08395217B1

公开(公告)日：2013-03-12

申请号：US13283031

申请日：2011-10-27

申请人： Kangguo Cheng ,  Joseph Ervin ,  Jeffrey B. Johnson ,  Pranita Kulkarni ,  Kevin McStay ,  Paul C. Parries ,  Chengwen Pei ,  Geng Wang ,  Yanli Zhang

发明人： Kangguo Cheng ,  Joseph Ervin ,  Jeffrey B. Johnson ,  Pranita Kulkarni ,  Kevin McStay ,  Paul C. Parries ,  Chengwen Pei ,  Geng Wang ,  Yanli Zhang

IPC分类号： H01L27/12 ,  H01L21/84

CPC分类号： H01L21/84 ,  H01L21/76289 ,  H01L21/823878 ,  H01L27/1203

摘要： A semiconductor device structure having an isolation region and method of manufacturing the same are provided. The semiconductor device structure includes a silicon-on-insulator (SOI) substrate. A plurality of gates is formed on the SOI substrate. The semiconductor device structure further includes trenches having sidewalls, formed between each of the plurality of gates. The semiconductor device structure further includes an epitaxial lateral growth layer formed in the trenches. The epitaxial lateral growth layer is grown laterally from the opposing sidewalls of the trenches, so that the epitaxial lateral growth layer encloses a portion of the trenches extended into the SOI substrate. The epitaxial lateral growth layer is formed in such way that it includes an air gap region overlying a buried dielectric layer of the SOI substrate.

摘要翻译： 提供了具有隔离区域的半导体器件结构及其制造方法。 半导体器件结构包括绝缘体上硅（SOI）衬底。 在SOI衬底上形成多个栅极。 半导体器件结构还包括形成在多个栅极中的每一个之间的具有侧壁的沟槽。 半导体器件结构还包括形成在沟槽中的外延横向生长层。 外延横向生长层从沟槽的相对侧壁横向生长，使得外延横向生长层包围延伸到SOI衬底中的沟槽的一部分。 外延横向生长层以这样的方式形成，使得其包括覆盖SOI衬底的掩埋介电层的气隙区域。

公开(公告)号：US20120068237A1

公开(公告)日：2012-03-22

申请号：US12886224

申请日：2010-09-20

申请人： Roger A. Booth, JR. ,  Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Geng Wang

发明人： Roger A. Booth, JR. ,  Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Geng Wang

IPC分类号： H01L27/108 ,  H01L21/8242

CPC分类号： H01L27/10876 ,  H01L21/84 ,  H01L27/10873 ,  H01L27/10894 ,  H01L27/1203 ,  H01L29/66181 ,  H01L29/945

摘要： After forming a planarization dielectric layer in a replacement gate integration scheme, disposable gate structures are removed and a stack of a gate dielectric layer and a gate electrode layer is formed within recessed gate regions. Each gate electrode structure is then recessed below a topmost surface of the gate dielectric layer. A dielectric metal oxide portion is formed above each gate electrode by planarization. The dielectric metal oxide portions and gate spacers are employed as a self-aligning etch mask in combination with a patterned photoresist to expose and metalize semiconductor surfaces of a source region and an inner electrode in each embedded memory cell structure. The metalized semiconductor portions form metal semiconductor alloy straps that provide a conductive path between the inner electrode of a capacitor and the source of an access transistor.

摘要翻译： 在替代栅极集成方案中形成平坦化介电层之后，去除一次性栅极结构，并且在凹入的栅极区内形成栅极电介质层和栅极电极层的堆叠。 然后，每个栅极电极结构凹陷在栅极电介质层的最上表面之下。 通过平面化形成在每个栅电极上方的介电金属氧化物部分。 电介质金属氧化物部分和栅极间隔物用作自对准蚀刻掩模与图案化的光致抗蚀剂组合以在每个嵌入的存储器单元结构中暴露和金属化源极区域和内部电极的半导体表面。 金属化半导体部分形成金属半导体合金带，其在电容器的内部电极和存取晶体管的源之间提供导电路径。

公开(公告)号：US20130207188A1

公开(公告)日：2013-08-15

申请号：US13369382

申请日：2012-02-09

申请人： Joseph Ervin ,  kangguo Cheng ,  Chengwen Pei ,  Geng Wang

发明人： Joseph Ervin ,  kangguo Cheng ,  Chengwen Pei ,  Geng Wang

IPC分类号： H01L29/786 ,  H01L21/336

CPC分类号： H01L21/76283 ,  H01L21/84 ,  H01L27/1203

摘要： A method of forming a semiconductor device including forming well trenches on opposing sides of a gate structure by removing portions of a semiconductor on insulator (SOI) layer of an semiconductor on insulator (SOI) substrate, wherein the base of the well trenches is provided by a surface of a buried dielectric layer of the SOI substrate and sidewalls of the well trenches are provided by a remaining portion of the SOI layer. Forming a dielectric fill material at the base of the well trenches, wherein the dielectric fill material is in contact with the sidewalls of the well trenches and at least a portion of the surface of the buried dielectric layer that provides the base of the well trenches. Forming a source region and a drain region in the well trenches with an in-situ doped epitaxial semiconductor material.

摘要翻译： 一种形成半导体器件的方法，包括通过去除绝缘体上半导体（SOI）衬底上的半导体绝缘体（SOI）层的部分，在栅极结构的相对侧上形成阱沟，其中阱沟的基极由 SOI衬底的掩埋介电层的表面和阱沟的侧壁由SOI层的剩余部分提供。 在阱沟的底部形成介电填充材料，其中介质填充材料与阱沟槽的侧壁和提供阱沟的基底的掩埋介电层的表面的至少一部分接触。 在原位掺杂的外延半导体材料的阱沟中形成源极区和漏极区。

公开(公告)号：US09484269B2

公开(公告)日：2016-11-01

申请号：US12822492

申请日：2010-06-24

申请人： Joseph Ervin ,  Jeffrey B. Johnson ,  Kevin McStay ,  Paul C. Parries ,  Chengwen Pei ,  Geng Wang ,  Yanli Zhang

发明人： Joseph Ervin ,  Jeffrey B. Johnson ,  Kevin McStay ,  Paul C. Parries ,  Chengwen Pei ,  Geng Wang ,  Yanli Zhang

IPC分类号： H01L27/12 ,  H01L21/8242 ,  H01L21/84 ,  H01L21/762 ,  H01L27/108

CPC分类号： H01L21/84 ,  H01L21/76237 ,  H01L27/10847 ,  H01L27/1203

摘要： Semiconductor structures and methods to control bottom corner threshold in a silicon-on-insulator (SOI) device. A method includes doping a corner region of a semiconductor-on-insulator (SOI) island. The doping includes tailoring a localized doping of the corner region to reduce capacitive coupling of the SOI island with an adjacent structure.

摘要翻译： 半导体结构和方法来控制绝缘体上硅（SOI）器件中的底角阈值。 一种方法包括掺杂绝缘体上半导体（SOI）岛的角区域。 掺杂包括定制角区域的局部掺杂以减少SOI岛与相邻结构的电容耦合。