公开(公告)号：US20110084781A1

公开(公告)日：2011-04-14

申请号：US12950519

申请日：2010-11-19

申请人： Emmanuel P. Quevy ,  David H. Bernstein

发明人： Emmanuel P. Quevy ,  David H. Bernstein

IPC分类号： H03H9/24 ,  H01L21/30

CPC分类号： B81C1/0069 ,  B81C1/00349 ,  B81C1/00523 ,  G02B6/358 ,  H03H3/0076 ,  H03H9/2405 ,  H03H9/2457 ,  H03H2009/02496 ,  H03H2009/2442 ,  Y10T29/42 ,  Y10T29/49005 ,  Y10T29/49165

摘要： MEMS resonators containing a first material and a second material to tailor the resonator's temperature coefficient of frequency (TCF). The first material has a different Young's modulus temperature coefficient than the second material. In one embodiment, the first material has a negative Young's modulus temperature coefficient and the second material has a positive Young's modulus temperature coefficient. In one such embodiment, the first material is a semiconductor and the second material is a dielectric. In a further embodiment, the quantity and location of the second material in the resonator is tailored to meet the resonator TCF specifications for a particular application. In an embodiment, the second material is isolated to a region of the resonator proximate to a point of maximum stress within the resonator. In a particular embodiment, the resonator includes a first material with a trench containing the second material.

摘要翻译： 包含第一材料和第二材料的MEMS谐振器以调整谐振器的频率温度系数（TCF）。 第一种材料具有与第二种材料不同的杨氏模量温度系数。 在一个实施例中，第一材料具有负杨氏模量温度系数，第二材料具有正的杨氏模量温度系数。 在一个这样的实施例中，第一材料是半导体，第二材料是电介质。 在另一实施例中，谐振器中的第二材料的数量和位置被调整为满足特定应用的谐振器TCF规格。 在一个实施例中，第二材料被隔离到谐振器附近的最大应力点处的谐振器的区域。 在特定实施例中，谐振器包括具有包含第二材料的沟槽的第一材料。

公开(公告)号：US07591201B1

公开(公告)日：2009-09-22

申请号：US11716285

申请日：2007-03-09

申请人： David H. Bernstein ,  Roger T. Howe ,  Emmanuel P. Quevy

发明人： David H. Bernstein ,  Roger T. Howe ,  Emmanuel P. Quevy

IPC分类号： F16H33/14

CPC分类号： H03H9/2457 ,  H03H3/0076 ,  H03H2009/02496 ,  Y10T74/11 ,  Y10T74/113

摘要： A MEMS structure having a compensated resonating member is described. In an embodiment, a MEMS structure comprises a resonating member coupled to a substrate by an anchor. A dynamic mass-load is coupled with the resonating member. The dynamic mass-load is provided for compensating a change in frequency of the resonating member by altering the moment of inertia of the resonating member by way of a positional change relative to the anchor.

摘要翻译： 描述了具有补偿谐振元件的MEMS结构。 在一个实施例中，MEMS结构包括通过锚固件耦合到衬底的谐振构件。 动态质量负载与谐振构件耦合。 提供动态质量负载，用于通过相对于锚的位置变化改变谐振构件的惯性矩来补偿谐振构件的频率变化。

公开(公告)号：US07514853B1

公开(公告)日：2009-04-07

申请号：US11801774

申请日：2007-05-10

申请人： Roger T. Howe ,  Emmanuel P. Quevy ,  David H. Bernstein

发明人： Roger T. Howe ,  Emmanuel P. Quevy ,  David H. Bernstein

IPC分类号： H01L23/34

CPC分类号： B81B3/0072 ,  B81B2201/0271 ,  H03H3/0076 ,  H03H9/02338 ,  H03H9/2431 ,  H03H9/2463 ,  H03H9/2473 ,  H03H2009/02354 ,  H03H2009/02496 ,  H03H2009/02503

摘要： A MEMS structure having a temperature-compensated resonating member is described. The MEMS structure comprises a stress inverter member coupled with a substrate. A resonating member is housed in the stress inverter member and is suspended above the substrate. The MEMS stress inverter member is used to alter the thermal coefficient of frequency of the resonating member by inducing a stress on the resonating member in response to a change in temperature.

摘要翻译： 描述具有温度补偿谐振元件的MEMS结构。 MEMS结构包括与基板耦合的应力逆变器部件。 谐振构件容纳在应力反转构件中并悬浮在基板上。 MEMS应力逆变器部件用于通过响应于温度变化在谐振部件上引起应力来改变谐振部件的频率的热系数。

公开(公告)号：US4133028A

公开(公告)日：1979-01-02

申请号：US728836

申请日：1976-10-01

申请人： David H. Bernstein

发明人： David H. Bernstein

IPC分类号： G06F15/78 ,  G06F13/00

CPC分类号： G06F15/7817

摘要： A data processing system having a particular configuration of interconnecting data paths among the data handling units thereof. The central processor unit of the system includes a skew-protected quadriport register file having two read and two write input ports as well as a separately located instruction register and a separately located memory address register. The first read port is connected to one of a pair of inputs to an arithmetic-logic unit and the second read port is connected to the other one of the pair of inputs to the arithmetic-logic unit and to the first write port of the register file. The output of the arithmetic-logic unit is connected to the memory address register and to a shifter unit, the shifted output thereupon being connected to the second write port of the register file. The system uses two separate buses for transferring data between the central processor unit and memory units and between the central processor unit and external input/output devices. A separate memory address unit transfers addresses from the memory address register to the memory units.

公开(公告)号：US08674775B2

公开(公告)日：2014-03-18

申请号：US13173449

申请日：2011-06-30

申请人： Mehrnaz Motiee ,  Emmanuel P. Quevy ,  David H. Bernstein

发明人： Mehrnaz Motiee ,  Emmanuel P. Quevy ,  David H. Bernstein

IPC分类号： H03B5/30

CPC分类号： H03H9/2457 ,  H03H9/2452 ,  H03H2009/02299 ,  H03H2009/02511

摘要： A microelectromechanical system (MEMS) device includes a resonator anchored to a substrate. The resonator includes a first strain gradient statically deflecting a released portion of the resonator in an out-of-plane direction with respect to the substrate. The resonator includes a first electrode anchored to the substrate. The first electrode includes a second strain gradient of a released portion of the first electrode. The first electrode is configured to electrostatically drive the resonator in a first mode that varies a relative amount of displacement between the resonator and the first electrode. The resonator may include a resonator anchor anchored to the substrate. The first electrode may include an electrode anchor anchored to the substrate in close proximity to the resonator anchor. The electrode anchor may be positioned relative to the resonator anchor to substantially decouple dynamic displacements of the resonator relative to the electrode from changes to the substrate.

摘要翻译： 微机电系统（MEMS）装置包括锚定到基板的谐振器。 谐振器包括使第一应变梯度在相对于衬底的平面外方向上静态偏转谐振器的释放部分。 谐振器包括锚定到基板的第一电极。 第一电极包括第一电极的释放部分的第二应变梯度。 第一电极被配置为以改变谐振器和第一电极之间的相对的位移量的第一模式静电驱动谐振器。 谐振器可以包括锚定到衬底的谐振器锚。 第一电极可以包括锚固到靠近谐振器锚的衬底的电极锚。 电极锚定件可以相对于谐振器锚固件定位，以基本上使谐振器相对于电极的动态位移与基板的变化相分离。

公开(公告)号：US08629739B2

公开(公告)日：2014-01-14

申请号：US13599240

申请日：2012-08-30

申请人： Emmanuel P. Quevy ,  David H. Bernstein ,  Mehrnaz Motiee

发明人： Emmanuel P. Quevy ,  David H. Bernstein ,  Mehrnaz Motiee

IPC分类号： H03H9/24 ,  H03H3/007 ,  H01L21/00

CPC分类号： H03H9/2457 ,  H03H3/0072 ,  H03H3/0076 ,  H03H9/02409 ,  H03H9/2463 ,  H03H2009/02299 ,  H03H2009/02307 ,  H03H2009/0233 ,  H03H2009/02472 ,  H03H2009/02511 ,  H03H2009/02519

摘要： A method of forming a microelectromechanical systems (MEMS) device includes forming an electrode on a substrate. The method includes forming a structural layer on the substrate. The structural layer is disposed about a perimeter of the electrode and has a residual film stress gradient. The method includes releasing the structural layer to form a resonator coupled to the substrate. The residual film stress gradient deflects a first portion of the resonator out of a plane defined by a surface of the electrode.

摘要翻译： 形成微机电系统（MEMS）器件的方法包括在衬底上形成电极。 该方法包括在衬底上形成结构层。 结构层围绕电极的周边设置并具有残余膜应力梯度。 该方法包括释放结构层以形成耦合到衬底的谐振器。 残余膜应力梯度将谐振器的第一部分偏离由电极表面限定的平面。

公开(公告)号：US20110260810A1

公开(公告)日：2011-10-27

申请号：US13173432

申请日：2011-06-30

申请人： Emmanuel P. Quevy ,  David H. Bernstein ,  Mehrnaz Motiee

发明人： Emmanuel P. Quevy ,  David H. Bernstein ,  Mehrnaz Motiee

IPC分类号： H03H9/24

CPC分类号： H03H9/2457 ,  H03H3/0072 ,  H03H3/0076 ,  H03H9/02409 ,  H03H9/2463 ,  H03H2009/02299 ,  H03H2009/02307 ,  H03H2009/0233 ,  H03H2009/02472 ,  H03H2009/02511 ,  H03H2009/02519

摘要： A microelectromechanical systems (MEMS) device includes a tuning electrode, a drive electrode, and a resonator. The resonator is anchored to a substrate and is configured to resonate in response to a signal on the drive electrode. The MEMS device includes a tuning plate coupled to the resonator and positioned above the tuning electrode. The tuning plate is configured to adjust a resonant frequency of the resonator in response to a voltage difference between the resonator and the tuning electrode. In at least one embodiment of the MEMS device, the tuning plate and the tuning electrode are configured to adjust the resonant frequency of the resonator substantially independent of the signal on the drive electrode.

摘要翻译： 微机电系统（MEMS）装置包括调谐电极，驱动电极和谐振器。 谐振器被锚固到衬底并且被配置为响应于驱动电极上的信号而谐振。 MEMS器件包括耦合到谐振器并且定位在调谐电极上方的调谐板。 调谐板被配置为响应谐振器和调谐电极之间的电压差来调节谐振器的谐振频率。 在MEMS器件的至少一个实施例中，调谐板和调谐电极被配置为基本上独立于驱动电极上的信号来调节谐振器的谐振频率。

公开(公告)号：US4766536A

公开(公告)日：1988-08-23

申请号：US15114

申请日：1987-02-17

申请人： James A. Wilson, Jr. ,  David H. Bernstein

发明人： James A. Wilson, Jr. ,  David H. Bernstein

IPC分类号： G06F13/374 ,  G06F13/26

CPC分类号： G06F13/374 ,  B60W2510/0241

摘要： A bus apparatus for interconnecting a plurality of nodes is disclosed. The nodes may comprise processors, input/output subsystems, or the like. Each node maintains a unique priority number; the priority numbers are determined independently by each node. Separate updating of the priority numbers occurs for acknowledgement packets as compared to data transmissions. This provides for quick, efficient acknowledgement of transmissions and does not unfairly penalize a popular receiving node. Two different interface circuits are described, one particularly suitable for use with an input/output subsystem, and the other for a processor.

摘要翻译： 公开了一种用于互连多个节点的总线装置。 节点可以包括处理器，输入/输出子系统等。 每个节点维护唯一的优先级数; 优先级数由每个节点独立确定。 与数据传输相比，确认分组发生优先级编号的单独更新。 这提供了对传输的快速，有效的确认，并且不会不公平地惩罚流行的接收节点。 描述了两个不同的接口电路，一个特别适用于输入/输出子系统，另一个用于处理器。

公开(公告)号：USRE30331E

公开(公告)日：1980-07-08

申请号：US19578

申请日：1979-03-12

申请人： Karsten Sorensen ,  David H. Bernstein ,  Michael B. Druke

发明人： Karsten Sorensen ,  David H. Bernstein ,  Michael B. Druke

IPC分类号： G06F1/04 ,  G06F9/22 ,  G06F9/312 ,  G06F9/40 ,  G06F13/42

CPC分类号： G06F9/30043 ,  G06F1/04 ,  G06F13/4243 ,  G06F9/226 ,  G06F9/4425

摘要： A data processing system in which the central processor unit operates asynchronously with one or more memory units independently of the operating speed of the memory units wherein the central processor timing signal and the memory timing signal have a predetermined phase relationship. The central processor unit is arranged to remain operative even when the memory unit is enabled unless it is disabled by a signal from the memory unit under preselected conditions. The central processor generates a plurality of operating instruction signals for transfer to the memory unit to permit the latter to perform its desired functions by enabling the memory unit, inhibiting the transfer of data from the memory unit to a data bus and permitting storage of data from the central processor unit when data is acceptable for such storage. A further operating instruction signal is generated at the central processor unit to permit data read from the memory unit to be modified at the central processor unit and stored in the memory unit after such modification. A further operating instruction signal is generated internally to the memory unit to prevent operation of all other memory devices in the memory unit when one of the memory devices therein is in operation.The logic for providing operation in a program or a non-program operating state is arranged to utilize one or more relatively small read-only-memory units for each of a plurality of selected groups of program and non-program operating states, each group using only one or two of such read-only-memory units for such purpose.The central processor unit further includes a unique arrangement interconnecting a skew protected, tri-state register file having two read and two write ports with an arithmetic logic unit having an output and an A-input and a B-input.

公开(公告)号：US4075692A

公开(公告)日：1978-02-21

申请号：US737416

申请日：1976-11-01

申请人： Karsten Sorensen ,  David H. Bernstein ,  Michael B. Druke

发明人： Karsten Sorensen ,  David H. Bernstein ,  Michael B. Druke

IPC分类号： G06F1/04 ,  G06F9/22 ,  G06F13/18 ,  G06F13/42 ,  G06F7/38

CPC分类号： G06F1/04 ,  G06F13/18 ,  G06F13/4243 ,  G06F9/226

摘要： A data processing system in which the central processor unit operates asynchronously with one or more memory units independently of the operating speed of the memory units wherein the central processor timing signal and the memory timing signal have a predetermined phase relationship. The central processor unit is arranged to remain operative even when the memory unit is enabled unless it is disabled by a signal from the memory unit under preselected conditions. The central processor generates a plurality of operating instruction signals for transfer to the memory unit to permit the latter to perform its desired functions by enabling the memory unit, inhibiting the transfer of data from the memory unit to a data bus and permitting storage of data from the central processor unit when data is acceptable for such storage. A further operating instruction signal is generated at the central processor unit to permit data read from the memory unit to be modified at the central processor unit and stored in the memory unit after such modification. A further operating instruction signal is generated internally to the memory unit to prevent operation of all other memory devices in the memory unit when one of the memory devices therein is in operation.The logic for providing operation in a program or a non-program operating state is arranged to utilize one or more relatively small read-only-memory units for each of a plurality of selected groups of program and non-program operating states, each group using only one or two of such read-only-memory units for such purpose.The central processor unit further includes a unique arrangement interconnecting a skew protected, tri-state register file having two read and two write ports with an arithmetic logic unit having an output and an A-input and a B-input.

摘要翻译： 一种数据处理系统，其中中央处理器单元与一个或多个存储器单元异步操作，独立于存储器单元的操作速度，其中中央处理器定时信号和存储器定时信号具有预定的相位关系。 中央处理器单元被布置成即使当存储器单元被使能时仍然保持操作，除非在预选条件下由存储器单元的信号禁用该处理器单元。 中央处理器产生多个操作指令信号以传送到存储器单元，以允许后者通过启用存储器单元来执行其期望的功能，从而阻止数据从存储器单元传送到数据总线并且允许数据从 中央处理器单元，当数据可接受这样的存储。 在中央处理器单元处产生进一步的操作指令信号，以便允许从存储器单元读取的数据在中央处理器单元处被修改，并且在这样的修改之后被存储在存储器单元中。 在存储器单元内部产生另外的操作指令信号，以防止存储器单元中的其中一个存储器件中的其中一个处于操作中时所有其他存储器件的操作。