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    Bipolar junction transistors with an air gap in the shallow trench isolation
    31.
    发明授权
    Bipolar junction transistors with an air gap in the shallow trench isolation 有权
    双极结晶体管与浅沟槽隔离有气隙

    公开(公告)号：US09231074B2

    公开(公告)日：2016-01-05

    申请号：US13946379

    申请日：2013-07-19

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Renata Camillo-Castillo ,  Vibhor Jain ,  Vikas K. Kaushal ,  Marwan H. Khater ,  Anthony K. Stamper

    IPC: H01L29/732 ,  H01L29/66 ,  H01L29/737 ,  H01L29/08 ,  H01L29/10

    CPC classification number: H01L29/66242 ,  H01L29/0649 ,  H01L29/0826 ,  H01L29/1004 ,  H01L29/7378

    Abstract: Device structures, fabrication methods, and design structures for a bipolar junction transistor. A trench isolation region is formed in a substrate. The trench isolation region is coextensive with a collector in the substrate. A base layer is formed on the collector and on a first portion of the trench isolation region. A dielectric layer is formed on the base layer and on a second portion of the trench isolation region peripheral to the base layer. After the dielectric layer is formed, the trench isolation region is at least partially removed to define an air gap beneath the dielectric layer and the base layer.

    Abstract translation: 双极结型晶体管的器件结构，制造方法和设计结构。 在衬底中形成沟槽隔离区。 沟槽隔离区域与衬底中的集电极共同延伸。 基底层形成在集电器和沟槽隔离区的第一部分上。 电介质层形成在基底层上和在基底层周边的沟槽隔离区域的第二部分上。 在形成电介质层之后，至少部分去除沟槽隔离区域以在电介质层和基底层下方形成气隙。

    STRUCTURES WITH AN AIRGAP AND METHODS OF FORMING SUCH STRUCTURES
    35.
    发明申请
    STRUCTURES WITH AN AIRGAP AND METHODS OF FORMING SUCH STRUCTURES 有权

    公开(公告)号：US20190273132A1

    公开(公告)日：2019-09-05

    申请号：US15911831

    申请日：2018-03-05

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Michael Zierak ,  Anthony K. Stamper ,  John J. Pekarik ,  Vibhor Jain

    IPC: H01L29/06 ,  H01L23/48 ,  H01L21/764 ,  H01L21/762 ,  H01L21/768

    Abstract: Structures that include an airgap and methods for forming a structure that includes an airgap. A layer stack is epitaxially grown on a substrate and includes a first semiconductor layer and a second semiconductor layer on a substrate. A plurality of openings are formed that extend through a device region of the first semiconductor layer to the second semiconductor layer. The second semiconductor layer is etched through the openings and selective to the substrate and the first semiconductor layer so as to form an airgap that is arranged in a vertical direction between the substrate and the device region. A device structure is formed in the device region of the first semiconductor layer.

    Structures with an airgap and methods of forming such structures
    36.
    发明授权
    Structures with an airgap and methods of forming such structures 有权

    公开(公告)号：US10388728B1

    公开(公告)日：2019-08-20

    申请号：US15911831

    申请日：2018-03-05

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Michael Zierak ,  Anthony K. Stamper ,  John J. Pekarik ,  Vibhor Jain

    IPC: H01L29/06 ,  H01L23/48 ,  H01L21/768 ,  H01L21/762 ,  H01L21/764

    Abstract: Structures that include an airgap and methods for forming a structure that includes an airgap. A layer stack is epitaxially grown on a substrate and includes a first semiconductor layer and a second semiconductor layer on a substrate. A plurality of openings are formed that extend through a device region of the first semiconductor layer to the second semiconductor layer. The second semiconductor layer is etched through the openings and selective to the substrate and the first semiconductor layer so as to form an airgap that is arranged in a vertical direction between the substrate and the device region. A device structure is formed in the device region of the first semiconductor layer.

    Methods of tuning current ratio in a current mirror for transistors formed with the same FEOL layout and a modified BEOL layout
    37.
    发明授权
    Methods of tuning current ratio in a current mirror for transistors formed with the same FEOL layout and a modified BEOL layout 有权

    公开(公告)号：US10331844B2

    公开(公告)日：2019-06-25

    申请号：US15290569

    申请日：2016-10-11

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Vibhor Jain ,  James W. Adkisson

    IPC: G06F17/50 ,  H01L27/082 ,  H01L21/8222 ,  H01L21/027

    Abstract: Methods for designing and fabricating a current mirror. A first layout is received for a first back-end-of-line (BEOL) stack that is coupled with an emitter of a bipolar junction transistor in a current mirror that has a first current ratio. A second layout for a second back-end-of-line (BEOL) stack, which differs from the first BEOL stack, is determined such that, when the second BEOL stack is coupled with the emitter of the bipolar junction transistor, the first current ratio is changed to a second current ratio. The change from the first current ratio to the second current ratio, which is based on the change from the first layout for the first BEOL stack to the second layout for the second BEOL stack, is accomplished without changing a front-end-of-line (FEOL) layout of the bipolar junction transistor.

    Optical through silicon via
    39.
    发明授权
    Optical through silicon via 有权

    公开(公告)号：US10197730B1

    公开(公告)日：2019-02-05

    申请号：US15806931

    申请日：2017-11-08

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Yves T. Ngu ,  Vibhor Jain ,  John J. Ellis-Monaghan ,  Sebastian Theodore Ventrone ,  Saurabh Sirohi

    IPC: G02B6/12 ,  G02B6/293 ,  G02F1/01 ,  G02F1/025

    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to optical via connections in chip-to-chip transmission in a 3D chip stack structure using an optical via, and methods of manufacture. The structure has a first wafer, including a first waveguide coupled to an optical resonator in the first wafer, and a second wafer, including a second waveguide, located over the first wafer. The structure also includes an optical via extending between the optical resonator of the first wafer and the second waveguide of the second wafer to optically couple the first and second waveguides.

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