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186 条记录 (耗时 0.037 秒)

    METHOD OF REDUCING CURRENT CONSUMPTION OF ELECTRIC HYDRAULIC POWER STEERING SYSTEM FOR VEHICLE
    31.
    发明申请
    METHOD OF REDUCING CURRENT CONSUMPTION OF ELECTRIC HYDRAULIC POWER STEERING SYSTEM FOR VEHICLE 有权
    降低电动液压动力转向系统电流消耗的方法

    公开(公告)号：US20090292420A1

    公开(公告)日：2009-11-26

    申请号：US12331967

    申请日：2008-12-10

    申请人： Hoon Choi

    发明人： Hoon Choi

    IPC分类号： B62D6/00

    CPC分类号： B62D5/065

    摘要： A method of reducing current consumption of an electric hydraulic power steering system for a vehicle includes determining whether or not a steering wheel is manipulated after an engine is started, and activating a sleep mode if it is determined that the steering wheel is not manipulated and if a vehicle speed is lower than a reference value for activating the sleep mode, or if it is determined that the steering wheel is manipulated and if an amount of current conducted in a motor, a vehicle speed and a steering angular velocity are lower than respective reference values for a predetermined time. According to the method, it is possible to reduce current consumption when the steering wheel is not manipulated and improve the vehicular fuel efficiency.

    摘要翻译： 一种降低用于车辆的电动液压动力转向系统的消耗电力的方法包括：确定在发动机起动之后是否操纵方向盘，并且如果确定方向盘未被操纵，则启动睡眠模式，并且如果 车速低于用于启动睡眠模式的参考值，或者如果确定方向盘被操纵，并且如果在电动机中传导的电流量，车速和转向角速度低于相应的参考值 值预定时间。 根据该方法，可以减少方向盘未被操纵时的电流消耗，并提高车辆燃料效率。

    DISPLAY APPARATUS FOR COMPENSATING OPTICAL PARAMETER USING FORWARD VOLTAGE OF LED AND METHOD THEREOF
    32.
    发明申请
    DISPLAY APPARATUS FOR COMPENSATING OPTICAL PARAMETER USING FORWARD VOLTAGE OF LED AND METHOD THEREOF 审中-公开
    用于使用LED的正向电压来补偿光学参数的显示装置及其方法

    公开(公告)号：US20090141049A1

    公开(公告)日：2009-06-04

    申请号：US12132336

    申请日：2008-06-03

    申请人： Tae-hyeun Ha ,  Rustam Abdulaev ,  Hoon Choi ,  Hyung-rae Kim

    发明人： Tae-hyeun Ha ,  Rustam Abdulaev ,  Hoon Choi ,  Hyung-rae Kim

    IPC分类号： G09G5/10

    CPC分类号： G09G3/3406 ,  G09G2310/0235 ,  G09G2320/041 ,  G09G2320/064

    摘要： A display apparatus for compensating an optical parameter, and a display method thereof are disclosed, the display apparatus including a display, an optical source unit, a voltage detection unit which measures the forward voltage of an optical source, and a control unit which controls driving of the optical source unit using a forward voltage of the at least one optical source. Accordingly, the variation of optical parameter is accurately compensated, and the cost for fabricating a temperature sensor and the time for measuring the temperature are reduced.

    摘要翻译： 公开了一种用于补偿光学参数的显示装置及其显示方法，所述显示装置包括显示器，光源单元，测量光源的正向电压的电压检测单元和控制驱动的控制单元 的光源单元，使用所述至少一个光源的正向电压。 因此，光学参数的变化被精确地补偿，制造温度传感器的成本和测量温度的时间被降低。

    Delay locked loop circuit with duty cycle correction and method of controlling the same
    33.
    发明申请
    Delay locked loop circuit with duty cycle correction and method of controlling the same 失效
    具有占空比校正的延迟锁定环路电路及其控制方法

    公开(公告)号：US20080191757A1

    公开(公告)日：2008-08-14

    申请号：US11878244

    申请日：2007-07-23

    申请人： Hoon Choi

    发明人： Hoon Choi

    IPC分类号： H03L7/085 ,  H03K5/05 ,  H03L7/08

    CPC分类号： H03K5/1565 ,  H03L7/0814 ,  H03L7/087

    摘要： A delay locked loop block receives external clocks to generate first internal clocks including a reference clock. An internal delay unit delays the first internal clocks to output second internal clocks, which are fed back to the delay locked loop block. The delay locked loop block adjusts delay time of the delay unit according to a phase difference between each second internal clock and the reference clock so that the second internal clocks are delay locked. A duty cycle correcting block corrects a duty cycle of each second internal clock and outputs a duty cycle corrected clock. An error determining unit compares a phase of each second internal clock with one another and, based on the comparison, feeds back a feedback clock including one of the duty cycle corrected clock or the second internal clock to the delay locked loop block.

    摘要翻译： 延迟锁定环路块接收外部时钟以产生包括参考时钟的第一内部时钟。 内部延迟单元延迟第一内部时钟以输出第二内部时钟，将其反馈到延迟锁定环路块。 延迟锁定环路块根据每个第二内部时钟和参考时钟之间的相位差来调整延迟单元的延迟时间，使得第二内部时钟被延迟锁定。 占空比校正块校正每个第二内部时钟的占空比，并输出占空比校正时钟。 误差确定单元将每个第二内部时钟的相位彼此进行比较，并且基于比较，将包括占空比校正时钟或第二内部时钟中的一个的反馈时钟反馈到延迟锁定环路块。

    Delay locked loop circuit
    34.
    发明申请
    Delay locked loop circuit 有权

    公开(公告)号：US20080130384A1

    公开(公告)日：2008-06-05

    申请号：US12010964

    申请日：2008-01-31

    申请人： Hoon Choi

    发明人： Hoon Choi

    IPC分类号： G11C7/00 ,  H03L7/06

    CPC分类号： H03L7/0814 ,  G11C7/1072 ,  G11C7/222 ,  H03L7/0805

    摘要： A DLL circuit and a synchronous memory device perform stable operation in a power down mode although the entry and exit into/from the power down mode is repeated rapidly. The synchronous memory device operates in a normal mode and a power down mode. A delay locked loop (DLL) generates a DLL clock having frozen locking information when exiting the power down mode. A controller precludes phase update operation of the DLL when a predetermined time passes after entering the power down mode to thereby obtain a time margin for a phase update operation undertaken in the normal mode.