公开(公告)号：US06756643B1

公开(公告)日：2004-06-29

申请号：US10459579

申请日：2003-06-12

Applicant: Krishnashree Achuthan ,  Shibly S. Ahmed ,  Haihong Wang ,  Bin Yu

Inventor： Krishnashree Achuthan ,  Shibly S. Ahmed ,  Haihong Wang ,  Bin Yu

IPC: H01L2976

CPC classification number: H01L29/785 ,  H01L21/3212 ,  H01L29/4908 ,  H01L29/66795 ,  H01L29/6681

Abstract: A FinFET-type semiconductor device includes a fin structure on which a relatively thin amorphous silicon layer and then an undoped polysilicon layer is formed. The semiconductor device may be planarized using a chemical mechanical polishing (CMP) in which the amorphous silicon layer acts as a stop layer to prevent damage to the fin structure.

Abstract translation: FinFET型半导体器件包括翅片结构，其上形成相对薄的非晶硅层，然后形成未掺杂的多晶硅层。 半导体器件可以使用化学机械抛光（CMP）进行平面化，其中非晶硅层用作阻挡层以防止损坏鳍结构。

公开(公告)号：US06756276B1

公开(公告)日：2004-06-29

申请号：US10335522

申请日：2002-12-31

Applicant: Qi Xiang ,  Jung-Suk Goo ,  Haihong Wang

Inventor： Qi Xiang ,  Jung-Suk Goo ,  Haihong Wang

IPC: H01L21336

CPC classification number: H01L29/66477 ,  H01L21/26586 ,  H01L29/1045 ,  H01L29/1054 ,  H01L29/665

Abstract: An n-type MOSFET (NMOS) is implemented on a substrate having an epitaxial layer of strained silicon formed on a layer of silicon germanium. The MOSFET includes first halo regions formed in the strained silicon layer that extent toward the channel region beyond the ends of shallow source and drain extensions. Second halo regions formed in the underlying silicon germanium layer extend toward the channel region beyond the ends of the shallow source and drain extensions and extend deeper into the silicon germanium layer than the shallow source and drain extensions. The p-type dopant of the first and second halo regions slows the high rate of diffusion of the n-type dopant of the shallow source and drain extensions through the silicon germanium toward the channel region. By counteracting the increased diffusion rate of the n-type dopant in this manner, the shallow source and drain extension profiles are maintained and the risk of degradation by short channel effects is reduced.

Abstract translation: 在具有形成在硅锗层上的应变硅的外延层的衬底上实施n型MOSFET（NMOS）。 MOSFET包括形成在应变硅层中的第一晕圈，其范围朝向超过浅源极和漏极延伸端的沟道区域。 形成在下面的硅锗层中的第二晕圈延伸到超过浅源极和漏极延伸端的沟道区，并且比浅源极和漏极延伸部更深地延伸到硅锗层中。 第一和第二晕圈区域的p型掺杂剂减缓了浅源极和漏极延伸部分的n型掺杂剂通过硅锗朝向沟道区的高扩散速率。 通过以这种方式抵消增加的n型掺杂剂的扩散速率，维持浅的源极和漏极延伸分布，并且降低由短沟道效应引起的退化的风险。

公开(公告)号：US06645797B1

公开(公告)日：2003-11-11

申请号：US10310926

申请日：2002-12-06

Applicant: Matthew S. Buynoski ,  Srikanteswara Dakshina-Murthy ,  Cyrus E. Tabery ,  Haihong Wang ,  Chih-Yuh Yang ,  Bin Yu

Inventor： Matthew S. Buynoski ,  Srikanteswara Dakshina-Murthy ,  Cyrus E. Tabery ,  Haihong Wang ,  Chih-Yuh Yang ,  Bin Yu

IPC: H01L2184

CPC classification number: H01L29/785 ,  H01L29/66795

Abstract: A method for forming a fin in a semiconductor device that includes a substrate, an insulating layer formed on the substrate, and a conductive layer formed on the insulating layer, includes forming a carbon layer over the conductive layer and forming a mask over the carbon layer. The method further includes etching the mask and carbon layer to form at least one structure, where the structure has a first width, reducing the width of the carbon layer in the at least one structure to a second width, depositing an oxide layer to surround the at least one structure, removing a portion of the oxide layer and the mask, removing the carbon layer to form an opening in a remaining portion of the oxide layer for each of the at least one structure, filling the at least one opening with conductive material, and removing the remaining portion of the oxide layer and a portion of the conductive layer to form the fin.

Abstract translation: 一种在半导体器件中形成翅片的方法，包括：衬底，形成在衬底上的绝缘层和形成在绝缘层上的导电层，包括在导电层上形成碳层，并在碳层上形成掩模 。 该方法还包括蚀刻掩模和碳层以形成至少一种结构，其中结构具有第一宽度，将至少一个结构中的碳层的宽度减小到第二宽度，沉积氧化物层以围绕 至少一个结构，去除所述氧化物层和所述掩模的一部分，除去所述碳层以在所述至少一个结构中的每一个结构的氧化物层的剩余部分中形成开口，用导电材料填充所述至少一个开口 并且去除氧化物层的剩余部分和导电层的一部分以形成翅片。

公开(公告)号：US08209283B1

公开(公告)日：2012-06-26

申请号：US12378819

申请日：2009-02-19

Applicant: Haihong Wang

Inventor： Haihong Wang

IPC: G06F17/30

CPC classification number: G06F17/30174 ,  Y10S707/99952

Abstract: Data replication includes generating replication data that is part of a replicated file system to be sent over a communication channel to a destination replication device; adding additional verification information to at least a portion of the replication data to prevent data corruption; and sending the replication data and the additional verification information over the communication channel to the destination replication device. The replication data with additional verification information is sent over the communication channel using a reliable protocol that allows the replication data to be verified by the reliable protocol at the destination replication device. The reliable protocol is a protocol capable of detecting most but not all data corruption introduced by the communication channel. The additional verification information includes information for verifying that replication data sent using the reliable protocol does not include data corruption that was introduced by the communication channel and undetected by the reliable protocol.

Abstract translation: 数据复制包括生成作为通过通信通道发送到目标复制设备的复制文件系统的一部分的复制数据; 向至少一部分复制数据添加其他验证信息，以防止数据损坏; 以及通过所述通信信道将所述复制数据和所述附加验证信息发送到所述目的地复制设备。 具有附加验证信息的复制数据通过通信通道使用可靠协议来发送，该协议允许复制数据由目的地复制设备上的可靠协议进行验证。 可靠的协议是能够检测通信信道引入的大多数但不是全部数据损坏的协议。 附加验证信息包括用于验证使用可靠协议发送的复制数据不包括由通信信道引入且不被可靠协议所检测到的数据损坏的信息。

公开(公告)号：US08008136B2

公开(公告)日：2011-08-30

申请号：US11379435

申请日：2006-04-20

Applicant: Ming-Ren Lin ,  Witold P. Maszara ,  Haihong Wang ,  Bin Yu

Inventor： Ming-Ren Lin ,  Witold P. Maszara ,  Haihong Wang ,  Bin Yu

IPC: H01L21/00 ,  H01L21/84

CPC classification number: H01L29/785 ,  H01L29/4908 ,  H01L29/66795 ,  H01L29/7842

Abstract: A method may include forming a gate electrode over a fin structure, depositing a first metal layer on a top surface of the gate electrode, performing a first silicide process to convert a portion of the gate electrode into a metal-silicide compound, depositing a second metal layer on a top surface of the metal-silicide compound, and performing a second silicide process to form a fully-silicided gate electrode.

Abstract translation: 一种方法可以包括在鳍结构上形成栅电极，在栅电极的顶表面上沉积第一金属层，执行第一硅化工艺以将栅电极的一部分转化为金属硅化物， 在金属硅化物化合物的顶表面上的金属层，并且执行第二硅化物处理以形成全硅化物栅电极。

公开(公告)号：US07541267B1

公开(公告)日：2009-06-02

申请号：US11765611

申请日：2007-06-20

Applicant: Haihong Wang ,  Shibly S. Ahmed ,  Ming-Ren Lin ,  Bin Yu

Inventor： Haihong Wang ,  Shibly S. Ahmed ,  Ming-Ren Lin ,  Bin Yu

IPC: H01L21/28

CPC classification number: H01L29/785 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/7842

Abstract: A method includes forming a first rectangular mesa from a layer of semiconducting material and forming a first dielectric layer around the first mesa. The method further includes forming a first rectangular mask over a first portion of the first mesa leaving an exposed second portion of the first mesa and etching the exposed second portion of the first mesa to produce a reversed T-shaped fin from the first mesa.

Abstract translation: 一种方法包括从半导体材料层形成第一矩形台面并在第一台面周围形成第一介电层。 该方法还包括在第一台面的第一部分上形成第一矩形掩模，离开第一台面的暴露的第二部分并蚀刻第一台面的暴露的第二部分以从第一台面产生反向的T形翅片。

公开(公告)号：US07262104B1

公开(公告)日：2007-08-28

申请号：US10857931

申请日：2004-06-02

Applicant: Haihong Wang ,  Shibly S. Ahmed ,  Bin Yu

Inventor： Haihong Wang ,  Shibly S. Ahmed ,  Bin Yu

IPC: H01L21/336

CPC classification number: H01L29/785 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795

Abstract: Multiple semiconductor devices are formed with different threshold voltages. According to one exemplary implementation, first and second semiconductor devices are formed and doped differently, resulting in different threshold voltages for the first and second semiconductor devices.

Abstract translation: 形成具有不同阈值电压的多个半导体器件。 根据一个示例性实施例，第一和第二半导体器件被形成和掺杂不同，导致第一和第二半导体器件的不同阈值电压。

公开(公告)号：US07259425B2

公开(公告)日：2007-08-21

申请号：US10348911

申请日：2003-01-23

Applicant: Judy Xilin An ,  Haihong Wang ,  Bin Yu

Inventor： Judy Xilin An ,  Haihong Wang ,  Bin Yu

IPC: H01L29/72

CPC classification number: H01L29/785 ,  H01L29/42384 ,  H01L29/66545 ,  H01L29/66795

Abstract: A triple gate metal-oxide semiconductor field-effect transistor (MOSFET) includes a fin structure, a first gate formed adjacent a first side of the fin structure, a second gate formed adjacent a second side of the fin structure opposite the first side, and a top gate formed on top of the fin structure. A gate around MOSFET includes multiple fins, a first sidewall gate structure formed adjacent one of the fins, a second sidewall gate structure formed adjacent another one of the fins, a top gate structure formed on one or more of the fins, and a bottom gate structure formed under one or more of the fins.

Abstract translation: 三栅极金属氧化物半导体场效应晶体管（MOSFET）包括翅片结构，邻近翅片结构的第一侧形成的第一栅极，与第一侧相对的翅片结构的第二侧附近形成的第二栅极，以及 形成在鳍结构顶部的顶门。 MOSFET周围的栅极包括多个散热片，邻近其中一个翅片形成的第一侧壁栅极结构，邻近另一个鳍片形成的第二侧壁栅极结构，形成在一个或多个翅片上的顶部栅极结构，以及底部栅极 在一个或多个翅片下形成的结构。

公开(公告)号：US07256455B2

公开(公告)日：2007-08-14

申请号：US10720166

申请日：2003-11-25

Applicant: Shibly S. Ahmed ,  Haihong Wang ,  Bin Yu

Inventor： Shibly S. Ahmed ,  Haihong Wang ,  Bin Yu

IPC: H01L27/12 ,  H01L29/786 ,  H01L29/76

CPC classification number: H01L29/785 ,  H01L29/42384 ,  H01L29/66545 ,  H01L29/66795

Abstract: A semiconductor device may include a substrate, an insulating layer formed on the substrate and a conductive fin formed on the insulating layer. The conductive fin may include a number of side surfaces and a top surface. The semiconductor device may also include a source region formed on the insulating layer adjacent a first end of the conductive fin and a drain region formed on the insulating layer adjacent a second end of the conductive fin. The semiconductor device may further include a metal gate formed on the insulating layer adjacent the conductive fin in a channel region of the semiconductor device.

Abstract translation: 半导体器件可以包括衬底，形成在衬底上的绝缘层和形成在绝缘层上的导电鳍。 导电翅片可以包括多个侧表面和顶表面。 半导体器件还可以包括形成在与导电鳍片的第一端相邻的绝缘层上的源极区域和形成在与导电鳍片的第二端相邻的绝缘层上的漏极区域。 半导体器件还可以包括在半导体器件的沟道区域中形成在与绝缘层相邻的导电鳍片上的金属栅极。

公开(公告)号：US07186599B2

公开(公告)日：2007-03-06

申请号：US10754540

申请日：2004-01-12

Applicant: Shibly S. Ahmed ,  Haihong Wang ,  Bin Yu

Inventor： Shibly S. Ahmed ,  Haihong Wang ,  Bin Yu

IPC: H01L21/00 ,  H01L21/84

CPC classification number: H01L29/785 ,  H01L29/66545 ,  H01L29/66795

Abstract: A method of forming a fin field effect transistor includes forming a fin and forming a source region on a first end of the fin and a drain region on a second end of the fin. The method further includes forming a dummy gate with a first semi-conducting material in a first pattern over the fin and forming a dielectric layer around the dummy gate. The method also includes removing the first semi-conducting material to leave a trench in the dielectric layer corresponding to the first pattern, thinning a portion of the fin exposed within the trench, and forming a metal gate within the trench.

Abstract translation: 形成鳍状场效应晶体管的方法包括：在鳍片的第一端上形成翅片并形成源极区域，在鳍片的第二端部形成漏极区域。 该方法还包括在鳍上形成具有第一图案的第一半导体材料的虚拟栅极，并在虚拟栅极周围形成介电层。 该方法还包括去除第一半导体材料以在对应于第一图案的电介质层中留下沟槽，使在沟槽内暴露的鳍片的一部分变薄，并在沟槽内形成金属栅极。