公开(公告)号：US07145216B2

公开(公告)日：2006-12-05

申请号：US10361989

申请日：2003-02-11

申请人： Ulrich Frey ,  Gunther Lehmann

发明人： Ulrich Frey ,  Gunther Lehmann

IPC分类号： H01L29/00

CPC分类号： G11C17/16

摘要： An antifuse apparatus includes first and second independent current paths connected to an antifuse. One of the current paths can be used to program the antifuse, and the other current path can be used to detect the status (programmed or not programmed) of the antifuse.

摘要翻译： 反熔丝设备包括连接到反熔丝的第一和第二独立电流路径。 可以使用其中一条路径来编程反熔丝，另一条电流路径可用于检测反熔丝的状态（已编程或未编程）。

公开(公告)号：US06798272B2

公开(公告)日：2004-09-28

申请号：US10187868

申请日：2002-07-02

申请人： Gunther Lehmann

发明人： Gunther Lehmann

IPC分类号： H01H3776

CPC分类号： G11C17/18 ,  G11C19/00

摘要： A sequential fuse latch device comprises a plurality of fuse latches, wherein each fuse latch is a data storage element, and a shift register comprising a plurality of pointer latches, wherein each pointer latch is connected to at least one fuse latch, wherein the shift register controls a sequential operation of the plurality of fuse latches.

摘要翻译： 顺序熔丝锁存装置包括多个熔丝锁存器，其中每个熔丝锁存器是数据存储元件，以及包括多个指针锁存器的移位寄存器，其中每个指针锁存器连接到至少一个熔丝锁存器，其中移位寄存器 控制多个熔丝锁存器的顺序操作。

公开(公告)号：US06353248B1

公开(公告)日：2002-03-05

申请号：US09562220

申请日：2000-04-28

申请人： Armin M Reith ,  Louis Hsu ,  Henning Haffner ,  Gunther Lehmann

发明人： Armin M Reith ,  Louis Hsu ,  Henning Haffner ,  Gunther Lehmann

IPC分类号： H01L2976

CPC分类号： H01L28/40 ,  H01L27/10861 ,  H01L27/10894 ,  H01L27/10897

摘要： A method to optimize the size and filling of decoupling capacitors for very large scale integrated circuits (VLSI) using existing lithographic fillers. The method combines the automatic or manual generation of lithographic fill patterns with the forming of the capacitors. According to the method, when the chip layout is about to be finished, all remaining empty space on the chip gets identified by a layout tool. Then, the closest power-supply nets get extracted. All power supplies and their combinations are sorted in a connection table which determines the appropriate types of capacitances once the power-supply nets closest to the empty spaces extracted from the layout. The empty spaces are then assigned appropriate decoupling capacitances. Decoupling capacitors generated by the method are suitable for VLSI power supplies for noise reduction.

摘要翻译： 使用现有的平版印刷填料，优化大型集成电路（VLSI）的去耦电容的尺寸和填充的方法。 该方法将自动或手动生成光刻填充图案与电容器的形成相结合。 根据该方法，当芯片布局即将完成时，芯片上的所有剩余空间都由布局工具识别。 然后，最近的电源网络被提取。 所有电源及其组合在连接表中排序，一旦电源网最接近从布局提取的空白空间中，则确定适当类型的电容。 然后空的空间被分配适当的去耦电容。 通过该方法产生的去耦电容适用于降低噪声的VLSI电源。

公开(公告)号：US06232154B1

公开(公告)日：2001-05-15

申请号：US09442890

申请日：1999-11-18

申请人： Armin M. Reith ,  Louis Hsu ,  Henning Haffner ,  Gunther Lehmann

发明人： Armin M. Reith ,  Louis Hsu ,  Henning Haffner ,  Gunther Lehmann

IPC分类号： H01L2182

CPC分类号： H01L28/40 ,  H01L27/10861 ,  H01L27/10894 ,  H01L27/10897

摘要： A method to optimize the size and filling of decoupling capacitors for very large scale integrated circuits (VLSI) using existing lithographic fillers. The method combines the automatic or manual generation of lithographic fill patterns with the forming of the capacitors. According to the method, when the chip layout is about to be finished, all remaining empty space on the chip gets identified by a layout tool. Then, the closest power-supply nets get extracted. All power supplies and their combinations are sorted in a connection table which determines the appropriate types of capacitances once the power-supply nets closest to the empty spaces extracted from the layout. The empty spaces are then assigned appropriate decoupling capacitances. Decoupling capacitors generated by the method are suitable for VLSI power supplies for noise reduction.

摘要翻译： 使用现有的平版印刷填料，优化大型集成电路（VLSI）的去耦电容的尺寸和填充的方法。 该方法将自动或手动生成光刻填充图案与电容器的形成相结合。 根据该方法，当芯片布局即将完成时，芯片上剩余的空余空间由布局工具识别。 然后，最近的电源网络被提取。 所有电源及其组合在连接表中排序，一旦电源网最接近从布局提取的空白空间中，则确定适当类型的电容。 然后空的空间被分配适当的去耦电容。 通过该方法产生的去耦电容适用于降低噪声的VLSI电源。

公开(公告)号：US07738305B2

公开(公告)日：2010-06-15

申请号：US11803852

申请日：2007-05-16

申请人： Gunther Lehmann ,  Yannick Martelloni ,  Jean-Yves Larguier ,  Gupta Siddharth

发明人： Gunther Lehmann ,  Yannick Martelloni ,  Jean-Yves Larguier ,  Gupta Siddharth

IPC分类号： G11C7/02

CPC分类号： G11C7/065 ,  G11C7/062 ,  G11C7/067 ,  G11C7/14 ,  G11C17/12

摘要： A read-out circuit for or in a ROM memory, comprises an input, a comparator circuit, a threshold setting, and a control signal generator for driving the threshold setting generator. A read signal can be coupled into the input. The read signal, depending on the information contained in the read signal, comprises a high signal level relative to a reference potential or a low signal level relative to a reference potential. The comparator circuit compares the read signal with a settable threshold, the threshold setting circuit is designed for setting the threshold of the comparator circuit relative to the high and low signal levels, and the control signal generator generates a control signal similar to the read signal.

摘要翻译： 用于或在ROM存储器中的读出电路包括用于驱动阈值设置发生器的输入，比较器电路，阈值设置和控制信号发生器。 读信号可以耦合到输入端。 取决于读取信号中包含的信息的读取信号包括相对于参考电位的高信号电平或相对于参考电位的低信号电平。 比较器电路将读取信号与可设置的阈值进行比较，阈值设置电路被设计用于相对于高和低信号电平设置比较器电路的阈值，并且控制信号发生器产生类似于读取信号的控制信号。

公开(公告)号：US07436721B2

公开(公告)日：2008-10-14

申请号：US11528079

申请日：2006-09-26

申请人： Gunther Lehmann ,  Yannick Martelloni ,  Devesh Dwivedi ,  Siddharth Gupta

发明人： Gunther Lehmann ,  Yannick Martelloni ,  Devesh Dwivedi ,  Siddharth Gupta

IPC分类号： G11C7/00

CPC分类号： G11C7/12 ,  G11C17/12

摘要： A method supplies voltage to a bit line of a memory device. The method includes precharging, with a precharging device, the bit line to an output potential, deactivating the precharging device during a read action related to the bit line, reading, during the read action, an information via the bit line, and routing, during the read action, a virtual voltage supply line to a supply potential of the memory device to supply voltage to memory cells of the memory device assigned to the bit line. The precharging device of the bit line is activated/deactivated as a function of the potential of the virtual voltage supply line.

摘要翻译： 一种方法向存储器件的位线提供电压。 该方法包括使用预充电装置将位线预充电到输出电位，在与位线有关的读取动作期间停用预充电装置，在读取动作期间通过位线读取信息，以及在路线期间进行路由 读取动作，将虚拟电压提供到存储器件的电源电位，以将电压提供给分配给位线的存储器件的存储器单元。 作为虚拟电压供给线的电位的函数，位线的预充电装置被激活/去激活。

公开(公告)号：US07394713B2

公开(公告)日：2008-07-01

申请号：US11380640

申请日：2006-04-27

申请人： Matthias Knopf ,  Stephan Kraus ,  Gunther Lehmann

发明人： Matthias Knopf ,  Stephan Kraus ,  Gunther Lehmann

IPC分类号： G11C7/00 ,  G11C5/00 ,  G11C11/34

CPC分类号： G11C17/18 ,  G11C7/24 ,  G11C11/005 ,  G11C11/4078 ,  G11C17/16 ,  G11C17/165

摘要： A memory device is provided, the memory device having a memory cell, a programming unit for programming the memory cell, and a switching unit for optionally connecting or isolating a terminal of the memory cell to or from a potential which serves for altering an electrical property of the memory cell and for thereby effecting an altered programming state of the memory cell.

摘要翻译： 提供了一种存储器件，该存储器件具有一个存储单元，一个用于编程该存储器单元的编程单元，以及用于可选地连接或隔离该存储器单元的端子或用于改变电性能的电位的开关单元 并且因此实现存储器单元的改变的编程状态。

公开(公告)号：US07366002B2

公开(公告)日：2008-04-29

申请号：US11267491

申请日：2005-11-04

申请人： Siddharth Gupta ,  Jean-Yves Larguier ,  Gunther Lehmann ,  Yannick Martelloni

发明人： Siddharth Gupta ,  Jean-Yves Larguier ,  Gunther Lehmann ,  Yannick Martelloni

IPC分类号： G11C17/00

CPC分类号： G11C7/1048 ,  G11C7/08 ,  G11C7/12 ,  G11C16/28 ,  G11C17/12 ,  G11C2207/005

摘要： It is proposed that bitline inversion coding data be integrally stored in the structure of a column multiplexer of a storage device. For this purpose, connections to a predefined potential are selectively provided at connection points, which are respectively assigned to one of the bitlines connected to the column multiplexer, in dependence on whether or not the assignment of a first state and of a second state of memory cells, connected to the bitline, to a binary value “0” and to a binary value “1” is inverted for the respective bitline. The connection points are connected to a common nodal point via switching means. The switching means are activated through control signals of the column multiplexer. Selection signals for activating inverter means, in order to effect a selective inversion of values read out from the memory cells, are generated in dependence on the signal level at the common nodal point. A precharging of the common nodal point is preferably effected between to read-out operations in each case, for which purpose precharging switching means are provided.

摘要翻译： 提出将位线反转编码数据一体地存储在存储装置的列多路复用器的结构中。 为此，在连接点上有选择地提供与预定义电位的连接，连接点根据是否分配第一状态和第二状态的存储器分别分配给连接到列多路复用器的位线之一 连接到位线的单元对于二进制值“0”和二进制值“1”反转。 连接点通过开关装置连接到公共节点。 切换装置通过列多路复用器的控制信号被激活。 根据公共节点处的信号电平，产生用于激活反相器装置的选择信号，以便实现从存储器单元读出的值的选择性反转。 优选地，在每种情况下对读出操作之间进行公共节点的预充电，为此，提供预充电开关装置。

公开(公告)号：US20060268616A1

公开(公告)日：2006-11-30

申请号：US11380640

申请日：2006-04-27

申请人： Matthias Knopf ,  Stephan Kraus ,  Gunther Lehmann

发明人： Matthias Knopf ,  Stephan Kraus ,  Gunther Lehmann

IPC分类号： G11C16/04

CPC分类号： G11C17/18 ,  G11C7/24 ,  G11C11/005 ,  G11C11/4078 ,  G11C17/16 ,  G11C17/165

摘要： A memory device is provided, the memory device having a memory cell, a programming unit for programming the memory cell, and a switching unit for optionally connecting or isolating a terminal of the memory cell to or from a potential which serves for altering an electrical property of the memory cell and for thereby effecting an altered programming state of the memory cell.

摘要翻译： 提供了一种存储器件，该存储器件具有一个存储单元，一个用于编程该存储器单元的编程单元，以及用于可选地连接或隔离该存储器单元的端子或用于改变电性能的电位的开关单元 并且因此实现存储器单元的改变的编程状态。

公开(公告)号：US20060133128A1

公开(公告)日：2006-06-22

申请号：US11267491

申请日：2005-11-04

申请人： Siddharth Gupta ,  Jean-Yves Larguier ,  Gunther Lehmann ,  Yannick Martelloni

发明人： Siddharth Gupta ,  Jean-Yves Larguier ,  Gunther Lehmann ,  Yannick Martelloni

IPC分类号： G11C17/00 ,  G11C7/10

CPC分类号： G11C7/1048 ,  G11C7/08 ,  G11C7/12 ,  G11C16/28 ,  G11C17/12 ,  G11C2207/005

摘要： It is proposed that bitline inversion coding data be integrally stored in the structure of a column multiplexer of a storage device. For this purpose, connections to a predefined potential are selectively provided at connection points, which are respectively assigned to one of the bitlines connected to the column multiplexer, in dependence on whether or not the assignment of a first state and of a second state of memory cells, connected to the bitline, to a binary value “0” and to a binary value “1” is inverted for the respective bitline. The connection points are connected to a common nodal point via switching means. The switching means are activated through control signals of the column multiplexer. Selection signals for activating inverter means, in order to effect a selective inversion of values read out from the memory cells, are generated in dependence on the signal level at the common nodal point. A precharging of the common nodal point is preferably effected between to read-out operations in each case, for which purpose precharging switching means are provided.

摘要翻译： 提出将位线反转编码数据一体地存储在存储装置的列多路复用器的结构中。 为此，在连接点上有选择地提供与预定义电位的连接，连接点根据是否分配第一状态和第二状态存储器分别分配给连接到列多路复用器的位线之一 连接到位线的单元对于二进制值“0”和二进制值“1”反转。 连接点通过开关装置连接到公共节点。 切换装置通过列多路复用器的控制信号被激活。 根据公共节点处的信号电平，产生用于激活反相器装置的选择信号，以便实现从存储器单元读出的值的选择性反转。 优选地，在每种情况下对读出操作之间进行公共节点的预充电，为此，提供预充电开关装置。