公开(公告)号：US07952132B2

公开(公告)日：2011-05-31

申请号：US12634406

申请日：2009-12-09

申请人： Daisuke Tsurumi ,  Mitsuhiro Noguchi ,  Haruhiko Koyama

发明人： Daisuke Tsurumi ,  Mitsuhiro Noguchi ,  Haruhiko Koyama

IPC分类号： H01L29/788

CPC分类号： H01L29/7881 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11517 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/788

摘要： A semiconductor memory device includes a source region, a drain region, a channel region, a charge storage layer, and a control gate electrode. The source region and drain region are formed separately from each other in a surface of a semiconductor substrate. The channel region is formed in the semiconductor substrate and located between the source region and the drain region. The charge storage layer is formed on the channel region with a first insulating film interposed therebetween. The control gate electrode is formed on the charge storage layer with a second insulating film interposed therebetween. The control gate has an upper corner portion rounded with a radius of curvature of 5 nm or more.

摘要翻译： 半导体存储器件包括源极区，漏极区，沟道区，电荷存储层和控制栅电极。 源极区域和漏极区域在半导体衬底的表面中彼此分开地形成。 沟道区形成在半导体衬底中并位于源极区和漏极区之间。 电荷存储层形成在通道区域上，其间插入有第一绝缘膜。 控制栅极电极形成在电荷存储层上，其间插入有第二绝缘膜。 控制门具有以5nm或更大的曲率半径圆化的上角部。

公开(公告)号：US07652319B2

公开(公告)日：2010-01-26

申请号：US11940838

申请日：2007-11-15

申请人： Daisuke Tsurumi ,  Mitsuhiro Noguchi ,  Haruhiko Koyama

发明人： Daisuke Tsurumi ,  Mitsuhiro Noguchi ,  Haruhiko Koyama

IPC分类号： H01L29/94

CPC分类号： H01L29/7881 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11517 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/788

摘要： A semiconductor memory device includes a source region, a drain region, a channel region, a charge storage layer, and a control gate electrode. The source region and drain region are formed separately from each other in a surface of a semiconductor substrate. The channel region is formed in the semiconductor substrate and located between the source region and the drain region. The charge storage layer is formed on the channel region with a first insulating film interposed therebetween. The control gate electrode is formed on the charge storage layer with a second insulating film interposed therebetween. The control gate has an upper corner portion rounded with a radius of curvature of 5 nm or more.

摘要翻译： 半导体存储器件包括源极区，漏极区，沟道区，电荷存储层和控制栅电极。 源极区域和漏极区域在半导体衬底的表面中彼此分开地形成。 沟道区形成在半导体衬底中并位于源极区和漏极区之间。 电荷存储层形成在通道区域上，其间插入有第一绝缘膜。 控制栅极电极形成在电荷存储层上，其间插入有第二绝缘膜。 控制门具有以5nm或更大的曲率半径圆化的上角部。

公开(公告)号：US20110193155A1

公开(公告)日：2011-08-11

申请号：US13092662

申请日：2011-04-22

申请人： Daisuke TSURUMI ,  Mitsuhiro Noguchi ,  Haruhiko Koyama

发明人： Daisuke TSURUMI ,  Mitsuhiro Noguchi ,  Haruhiko Koyama

IPC分类号： H01L29/792

CPC分类号： H01L29/7881 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11517 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/788

摘要： A semiconductor memory device includes a source region, a drain region, a channel region, a charge storage layer, and a control gate electrode. The source region and drain region are formed separately from each other in a surface of a semiconductor substrate. The channel region is formed in the semiconductor substrate and located between the source region and the drain region. The charge storage layer is formed on the channel region with a first insulating film interposed therebetween. The control gate electrode is formed on the charge storage layer with a second insulating film interposed therebetween. The control gate has an upper corner portion rounded with a radius of curvature of 5 nm or more.

摘要翻译： 半导体存储器件包括源极区，漏极区，沟道区，电荷存储层和控制栅电极。 源极区域和漏极区域在半导体衬底的表面中彼此分开地形成。 沟道区形成在半导体衬底中并位于源极区和漏极区之间。 电荷存储层形成在通道区域上，其间插入有第一绝缘膜。 控制栅极电极形成在电荷存储层上，其间插入有第二绝缘膜。 控制门具有以5nm或更大的曲率半径圆化的上角部。

公开(公告)号：US20100084703A1

公开(公告)日：2010-04-08

申请号：US12634406

申请日：2009-12-09

申请人： Daisuke TSURUMI ,  Mitsuhiro Noguchi ,  Haruhiko Koyama

发明人： Daisuke TSURUMI ,  Mitsuhiro Noguchi ,  Haruhiko Koyama

IPC分类号： H01L29/792

CPC分类号： H01L29/7881 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11517 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/788

摘要： A semiconductor memory device includes a source region, a drain region, a channel region, a charge storage layer, and a control gate electrode. The source region and drain region are formed separately from each other in a surface of a semiconductor substrate. The channel region is formed in the semiconductor substrate and located between the source region and the drain region. The charge storage layer is formed on the channel region with a first insulating film interposed therebetween. The control gate electrode is formed on the charge storage layer with a second insulating film interposed therebetween. The control gate has an upper corner portion rounded with a radius of curvature of 5 nm or more.

摘要翻译： 半导体存储器件包括源极区，漏极区，沟道区，电荷存储层和控制栅电极。 源极区域和漏极区域在半导体衬底的表面中彼此分开地形成。 沟道区形成在半导体衬底中并位于源极区和漏极区之间。 电荷存储层形成在通道区域上，其间插入有第一绝缘膜。 控制栅极电极形成在电荷存储层上，其间插入有第二绝缘膜。 控制门具有以5nm或更大的曲率半径圆化的上角部。

公开(公告)号：US20080116503A1

公开(公告)日：2008-05-22

申请号：US11940838

申请日：2007-11-15

申请人： Daisuke Tsurumi ,  Mitsuhiro Noguchi ,  Haruhiko Koyama

发明人： Daisuke Tsurumi ,  Mitsuhiro Noguchi ,  Haruhiko Koyama

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L29/7881 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11517 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/788

摘要： A semiconductor memory device includes a source region, a drain region, a channel region, a charge storage layer, and a control gate electrode. The source region and drain region are formed separately from each other in a surface of a semiconductor substrate. The channel region is formed in the semiconductor substrate and located between the source region and the drain region. The charge storage layer is formed on the channel region with a first insulating film interposed therebetween. The control gate electrode is formed on the charge storage layer with a second insulating film interposed therebetween. The control gate has an upper corner portion rounded with a radius of curvature of 5 nm or more.

摘要翻译： 半导体存储器件包括源极区，漏极区，沟道区，电荷存储层和控制栅电极。 源极区域和漏极区域在半导体衬底的表面中彼此分开地形成。 沟道区形成在半导体衬底中并位于源极区和漏极区之间。 电荷存储层形成在通道区域上，其间插入有第一绝缘膜。 控制栅极电极形成在电荷存储层上，其间插入有第二绝缘膜。 控制门具有以5nm或更大的曲率半径圆化的上角部。

公开(公告)号：US08395922B2

公开(公告)日：2013-03-12

申请号：US13035134

申请日：2011-02-25

申请人： Mitsuhiro Noguchi ,  Kenji Sawamura ,  Takeshi Kamigaichi ,  Katsuaki Isobe

发明人： Mitsuhiro Noguchi ,  Kenji Sawamura ,  Takeshi Kamigaichi ,  Katsuaki Isobe

IPC分类号： G11C5/06

CPC分类号： G11C5/025 ,  G11C16/0483 ,  G11C16/26

摘要： According to one embodiment, a semiconductor memory device includes a memory cell array, a first sense amplifier circuit, and a second sense amplifier circuit. The memory cell array includes a plurality of first memory cell units, a plurality of second memory cell units, a plurality of first interconnects, and a plurality of second interconnects. The first sense amplifier circuit is connected to the plurality of first interconnects. The second sense amplifier circuit is connected to the plurality of second interconnects. Heights of upper surfaces of interconnects are equal. At least one of a width of each of the plurality of second interconnects along a second direction perpendicular to the first direction and a thickness of each of the plurality of second interconnects along a third direction perpendicular to the first direction and the second direction is set smaller than each of the plurality of first interconnects, and the first sense amplifier circuit and the second sense amplifier circuit are disposed to face each other across the memory cell array.

摘要翻译： 根据一个实施例，半导体存储器件包括存储单元阵列，第一读出放大器电路和第二读出放大器电路。 存储单元阵列包括多个第一存储单元单元，多个第二存储单元单元，多个第一互连和多个第二互连。 第一读出放大器电路连接到多个第一互连。 第二读出放大器电路连接到多个第二互连。 互连上表面的高度相等。 沿着与第一方向垂直的第二方向的多个第二互连件的每一个的宽度中的至少一个以及沿着垂直于第一方向和第二方向的第三方向的多个第二互连件中的每一个的厚度被设置得较小 并且第一读出放大器电路和第二读出放大器电路被设置为跨越存储单元阵列彼此面对。

公开(公告)号：US08327229B2

公开(公告)日：2012-12-04

申请号：US12818709

申请日：2010-06-18

申请人： Mitsuhiro Noguchi

发明人： Mitsuhiro Noguchi

IPC分类号： G11C29/00

CPC分类号： G11C16/3427 ,  G06F11/1068 ,  G11C7/1006 ,  G11C8/04 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3418 ,  G11C19/00 ,  G11C29/00

摘要： A data memory system is provided which includes a nonvolatile memory cell array, an error correction code generation circuit, an error correction code decoding circuit, and a first circuit. The nonvolatile memory cell array includes a plurality of memory cells which store digital data each having at least a value of “1” or “0” as a charge of a charge accumulation layer included in each memory cell, and use a difference between charges of the accumulation layer as a writing bit or an erasing bit. The nonvolatile memory cell array erases memory cells in units of pages, each page being formed of adjacent memory cells included in the plurality of memory cells.

摘要翻译： 提供一种包括非易失性存储单元阵列，纠错码产生电路，纠错码解码电路和第一电路的数据存储系统。 非易失性存储单元阵列包括多个存储单元，其存储每个具有至少1或0值的数字数据作为每个存储单元中包含的电荷累积层的电荷，并且使用积累层的电荷之间的差作为 写位或擦除位。 非易失性存储单元阵列以页为单位擦除存储单元，每页由包含在多个存储单元中的相邻存储单元形成。

公开(公告)号：US08185802B2

公开(公告)日：2012-05-22

申请号：US12369889

申请日：2009-02-12

申请人： Mitsuhiro Noguchi

发明人： Mitsuhiro Noguchi

IPC分类号： G11C29/00

CPC分类号： G11C16/3427 ,  G06F11/1068 ,  G11C7/1006 ,  G11C8/04 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3418 ,  G11C19/00 ,  G11C29/00

摘要： A data memory system includes a nonvolatile memory cell array which includes a plurality of memory cells, a page adjacently formed by the plurality of memory cells being collectively erased in the nonvolatile memory cell, at least binary pieces of digital data of “1” and “0” being stored as charges of a charge accumulation layer in the memory cell, a programming bit and an erasing bit being formed by a difference between the charges of the charge accumulation layer. And the system includes an error correcting code generation circuit, an error correcting code decoding circuit, and a code conversion circuit.

摘要翻译： 一种数据存储器系统包括：非易失性存储单元阵列，其包括多个存储单元，由所述多个存储器单元相邻形成的页面在所述非易失性存储单元中被共同擦除;至少二进制数字数据“1”和“ 0“作为电荷累积层的电荷存储在存储单元中，由电荷累积层的电荷之间的差异形成的编程位和擦除位。 该系统包括纠错码产生电路，纠错码解码电路和代码转换电路。

公开(公告)号：US20120037973A1

公开(公告)日：2012-02-16

申请号：US13281083

申请日：2011-10-25

申请人： Kenji GOMIKAWA ,  Tadashi Iguchi ,  Mitsuhiro Noguchi ,  Shoichi Watanabe

发明人： Kenji GOMIKAWA ,  Tadashi Iguchi ,  Mitsuhiro Noguchi ,  Shoichi Watanabe

IPC分类号： H01L29/788 ,  H01L29/792

CPC分类号： H01L29/792 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： A memory cell includes a floating gate electrode, a first inter-electrode insulating film and a control gate electrode. A peripheral transistor includes a lower electrode, a second inter-electrode insulating film and an upper electrode. The lower electrode and the upper electrode are electrically connected via an opening provided on the second inter-electrode insulating film. The first and second inter-electrode insulating films include a high-permittivity material, the first inter-electrode insulating film has a first structure, and the second inter-electrode insulating film has a second structure different from the first structure.

摘要翻译： 存储单元包括浮置栅电极，第一电极间绝缘膜和控制栅电极。 外围晶体管包括下电极，第二电极间绝缘膜和上电极。 下电极和上电极通过设置在第二电极间绝缘膜上的开口电连接。 第一和第二电极间绝缘膜包括高电容率材料，第一电极间绝缘膜具有第一结构，第二电极间绝缘膜具有与第一结构不同的第二结构。

公开(公告)号：US20120012909A1

公开(公告)日：2012-01-19

申请号：US13241965

申请日：2011-09-23

申请人： Mitsuhiro Noguchi ,  Kenji Gomikawa

发明人： Mitsuhiro Noguchi ,  Kenji Gomikawa

IPC分类号： H01L27/115

CPC分类号： G11C16/24 ,  G11C16/30 ,  H01L27/0207 ,  H01L27/0222 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11529

摘要： A semiconductor device includes MOS transistors, capacitor elements, a voltage generating circuit, a contact plug, and a memory cell. The MOS transistor and the capacitor element are formed on a first one of the element regions and a second one of the element regions, respectively. In the voltage generating circuit, current paths of the MOS transistors are series-connected and the capacitor elements are connected to the source or drain of the MOS transistors. The contact plug is formed on the source or the drain to connect the MOS transistors or one of the MOS transistors and one of the capacitor elements. A distance between the gate and the contact plug both for a first one of the MOS transistors located in the final stage in the series connection is larger than that for a second one of the MOS transistors located in the initial stage in the series connection.

摘要翻译： 半导体器件包括MOS晶体管，电容器元件，电压产生电路，接触插头和存储单元。 MOS晶体管和电容器元件分别形成在第一元件区域和第二元件区域中。 在电压产生电路中，MOS晶体管的电流路径串联连接，并且电容器元件连接到MOS晶体管的源极或漏极。 接触插塞形成在源极或漏极上，以连接MOS晶体管或MOS晶体管之一以及电容器元件之一。 位于串联连接的最后级的MOS晶体管的栅极和接触插塞之间的距离大于串联连接中位于初始阶段的第二个MOS晶体管的距离。