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公开(公告)号：US08513607B2
公开(公告)日：2013-08-20
申请号：US13085264
申请日：2011-04-12
IPC分类号： G01J5/02
CPC分类号： H01Q3/26 , G01S7/288 , G01S13/426
摘要： A method for determining the position of a target is provided. Several emitted pulses of terahertz radiations are emitted from a phased array (which has several transceivers) in consecutive cycles (typically). These emitted pulses are generally configured to be reflected by a target so as to be received by the phased array within a scan range (which includes a digitization window with several sampling periods). Output signals from each of the transceivers are then combined to generate a combined signal for each cycle. The combined signal in each sampling period within the digitization window for emitted pulses is averaged to generate an averaged signal for each sampling period within the digitization window. These averaged signals are then digitized.
摘要翻译： 提供了一种用于确定目标位置的方法。 几个发射的太赫兹辐射脉冲从相控阵列（其具有几个收发器）以连续的周期（通常）发射。 这些发射脉冲通常被配置为被目标物反射，以便在扫描范围内包括相控阵列（其包括具有多个采样周期的数字化窗口）。 然后将来自每个收发器的输出信号组合以产生每个周期的组合信号。 在发射脉冲的数字化窗口内的每个采样周期中的组合信号被平均以产生数字化窗口内的每个采样周期的平均信号。 然后将这些平均信号数字化。
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公开(公告)号：US08472884B2
公开(公告)日：2013-06-25
申请号：US12878484
申请日：2010-09-09
IPC分类号： H04B17/00
CPC分类号： H03F3/2171 , H01Q1/2283 , H01Q3/26 , H03B5/1212 , H03B5/1228 , H03B2200/0074 , H03F3/245 , H03F3/45188 , H03L7/18
摘要： Microelectronics have now developed to the point where radiation within the terahertz frequency range can be generated and used. Here, an integrated circuit or IC is provided that includes a phased array radar system, which uses terahertz radiation. In order to accomplish this, several features are employed; namely, a lower frequency signal is propagated to transceivers, which multiplies the frequency up to the desired frequency range. To overcome the losses from the multiplication, an injection locked voltage controlled oscillator (ILVCO) is used, and a high frequency power amplifier (PA) can then be used to amplify the signal for transmission.
摘要翻译： 微电子学已经发展到可以产生和使用太赫兹频率范围内的辐射的地步。 这里，提供了一种集成电路或IC，其包括使用太赫兹辐射的相控阵雷达系统。 为了实现这一点，采用了几个特征; 即，较低频率信号被传播到收发器，收发机将频率乘以所需的频率范围。 为了克服乘法的损耗，使用注入锁定电压控制振荡器（ILVCO），然后可以使用高频功率放大器（PA）来放大信号进行传输。
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公开(公告)号：US20120322400A1
公开(公告)日：2012-12-20
申请号：US13161718
申请日：2011-06-16
IPC分类号： H04B1/16
CPC分类号： H03D7/00 , H03D7/1441 , H03D7/1466 , H03D2200/0023
摘要： Blixers, which are a relatively recent development, have not be studied as extensively as many older circuit designs. Here, a blixer is provided that improves linearity and reduces noise over other conventional blixer designs. To accomplish this, the blixer provided here uses a differential amplifier and/or a dummy path within its mixing circuit to perform noise reduction (and improve linearity).
摘要翻译： 作为相对较新的开发的混合动力车，并没有像现在很多旧的电路设计一样被研究。 在这里，提供了一种混合器，可以提高线性度，并降低噪音超过其他传统的混合器设计。 为了实现这一点，这里提供的混合器在其混合电路中使用差分放大器和/或虚拟路径来执行降噪（并提高线性度）。
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公开(公告)号：US08332700B2
公开(公告)日：2012-12-11
申请号：US13330178
申请日：2011-12-19
申请人： Lee D. Whetsel , Baher S. Haroun , Brian J. Lasher , Anjali Kinra
发明人： Lee D. Whetsel , Baher S. Haroun , Brian J. Lasher , Anjali Kinra
IPC分类号： G01R31/28
CPC分类号： G01R31/3177 , G01R31/31727 , G01R31/318555
摘要： IEEE 1149.1 Test Access Ports (TAPs) may be utilized at both IC and intellectual property core design levels. TAPs serve as serial communication ports for accessing a variety of embedded circuitry within ICs and cores including; IEEE 1149.1 boundary scan circuitry, built in test circuitry, internal scan circuitry, IEEE 1149.4 mixed signal test circuitry, IEEE P5001 in-circuit emulation circuitry, and IEEE P1532 in-system programming circuitry. Selectable access to TAPs within ICs is desirable since in many instances being able to access only the desired TAP(s) leads to improvements in the way testing, emulation, and programming may be performed within an IC. A TAP linking module is described that allows TAPs embedded within an IC to be selectively accessed using 1149.1 instruction scan operations.
摘要翻译： IEEE 1149.1测试接入端口（TAP）可用于IC和知识产权核心设计级别。 TAP用作用于访问IC和核心内的各种嵌入式电路的串行通信端口，包括： IEEE 1149.1边界扫描电路，内置测试电路，内部扫描电路，IEEE 1149.4混合信号测试电路，IEEE P5001在线仿真电路和IEEE P1532系统编程电路。 可选择地访问IC内的TAP是理想的，因为在许多情况下，仅能够访问期望的TAP导致在IC内可以执行测试，仿真和编程的方式的改进。 描述了一种TAP链接模块，其允许使用1149.1指令扫描操作来选择性地访问嵌入在IC内的TAP。
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公开(公告)号：US08275342B2
公开(公告)日：2012-09-25
申请号：US12871626
申请日：2010-08-30
CPC分类号： H01P5/184 , H03D7/1441 , H03D7/1458 , H03D7/1466 , H03D7/165 , H03D2200/0023
摘要： At very high frequencies, generally above 100 GHz, the performance of traditional radio frequency (RF) circuitry begins to significantly limit performance. An example is the hybrid coupler, which can have a relatively narrow 90° bandwidth in these frequency ranges. Here, however, a branch-line hybrid coupler (which has been integrated into a quadrature downconversion mixer) has been modified. Namely, an adjustable impedance network has been coupled to isolation port (which has traditionally been terminated) to substantially increase the tuning range and expand the bandwidth of the quadrature mixer within these very high frequency ranges.
摘要翻译： 在非常高的频率（通常在100GHz以上），传统射频（RF）电路的性能开始显着地限制性能。 一个例子是混合耦合器，其在这些频率范围内可以具有相对窄的90°带宽。 然而，这里已经修改了分支线路混合耦合器（其已被集成到正交下变频混频器中）。 也就是说，可调阻抗网络已经耦合到隔离端口（传统上已被终止），以显着增加调谐范围并且在这些非常高的频率范围内扩大正交混频器的带宽。
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公开(公告)号：US20120086589A1
公开(公告)日：2012-04-12
申请号：US12899205
申请日：2010-10-06
摘要： Traditionally, pipelined continuous-time (CT) sigma-delta modulators (SDM) have been difficult to build due at least in part to the difficulties in calibrating the pipeline. Here, however, a pipelined CT SDM is provided that has an architecture that is conducing to being calibrated. Namely, the system includes a digital filter and other features that can be adjusted to account for input imbalance errors and well as quantization leakage noise.
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37.发明授权Single-ended polar transmitting circuit with current salvaging and substantially constant bandwidth 有权单端极性发射电路，具有当前的抢救和基本上恒定的带宽公开(公告)号：US08111181B2
公开(公告)日：2012-02-07
申请号：US12577075
申请日：2009-10-09
IPC分类号： H03M1/66
CPC分类号： H03C5/00 , H03D7/1441 , H03D7/1458 , H03D2200/0023
摘要： An embodiment of the invention provides a single-ended polar transmitting circuit. The single-ended polar transmitting circuit comprises a DAC, a differential-to-single-ended converter, a GmC filter and a load. The GmC filter comprises two gain stages, two filters, two switching devices, a translinear loop and a current mirror. When a second clock signal is high, a first current is conducted through the load, a second switching device and a second gain stage. When a first clock signal is high, a second current is conducted through a first switching device and the second gain stage. The first gain stage has a transconductance Gm1 and the second gain stage has a transconductance Gm2. The bandwidth of the GmC filter is approximately equal to the square root of the quantity (Gm1*Gm2)/(C1*C2). The bandwidth of the GmC filter is substantially a constant value.
摘要翻译： 本发明的实施例提供了一种单端极性发射电路。 单端极性发射电路包括DAC，差分到单端转换器，GmC滤波器和负载。 GmC滤波器包括两个增益级，两个滤波器，两个开关器件，一个跨线回路和一个电流镜。 当第二时钟信号为高时，通过负载，第二开关装置和第二增益级传导第一电流。 当第一时钟信号为高时，通过第一开关器件和第二增益级传导第二电流。 第一增益级具有跨导Gm1，第二增益级具有跨导Gm2。 GmC滤波器的带宽近似等于量的平方根（Gm1 * Gm2）/（C1 * C2）。 GmC滤波器的带宽基本上是一个恒定值。
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38.发明授权Augmentation instruction shift register with serial and two parallel inputs 有权扩展指令移位寄存器，具有串行和两个并行输入公开(公告)号：US07925942B2
公开(公告)日：2011-04-12
申请号：US12539373
申请日：2009-08-11
申请人： Baher S. Haroun , Lee D. Whetsel
发明人： Baher S. Haroun , Lee D. Whetsel
IPC分类号： G01R31/28
CPC分类号： G01R31/3177 , G01R31/2851 , G01R31/318536 , G01R31/318544 , G01R31/318555 , G01R31/318558 , G11C29/46
摘要： An architecture for testing a plurality of circuits on an integrated circuit is described. The architecture includes a TAP Linking Module located between test pins on the integrated circuit and 1149.1 Test Access Ports (TAP) of the plurality of circuits to be tested. The TAP Linking Module operates in response to 1149.1 scan operations from a tester connected to the test pins to selectively switch between 1149.1 TAPs to enable test access between the tester and plurality of circuits. The TAP Linking Module's 1149.1 TAP switching operation is based upon augmenting 1149.1 instruction patterns to affix an additional bit or bits of information which is used by the TAP Linking Module for performing the TAP switching operation.
摘要翻译： 描述了用于在集成电路上测试多个电路的架构。 该架构包括位于集成电路的测试引脚之间的TAP链接模块和待测试的多个电路的1149.1测试访问端口（TAP）。 TAP链接模块响应来自连接到测试引脚的测试仪的1149.1扫描操作，以选择性地在1149.1 TAP之间切换，以使测试仪和多个电路之间能够进行测试。 TAP链接模块的1149.1 TAP切换操作基于增加1149.1指令模式，以附加TAP链接模块用于执行TAP切换操作的附加位或位信息。
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公开(公告)号：US07915905B2
公开(公告)日：2011-03-29
申请号：US12761544
申请日：2010-04-16
申请人： Baher S. Haroun , Gaurav Chandra , Vijaya Bhaskar Rentala , Venkatesh Srinivasan , Hisashi Shichijo , Krishnaswamy Nagaraj
发明人： Baher S. Haroun , Gaurav Chandra , Vijaya Bhaskar Rentala , Venkatesh Srinivasan , Hisashi Shichijo , Krishnaswamy Nagaraj
IPC分类号： G01R31/00
摘要： In an apparatus and method for monitoring defects in wafers, a monitoring circuit is fabricated on an area of each one of the wafers. The monitoring circuit includes representative devices that replicate similar devices located in a die area of the wafers. Defects if present in the representative devices contribute to a generation of a noise, thereby causing an imbalance in a differential signal measurable across selected ones of the representative devices. A digitizing circuit that uses a common mode voltage as a reference to measure the imbalance digitizes the differential signal to a digital signal, the digital signal being indicative of the noise generated by the defects. The digital signal is stored over a configurable time interval to form a digital bit stream. The digital bit stream is compared to a reference to determine whether the defeats are within an allowable range.
摘要翻译： 在用于监测晶片中的缺陷的装置和方法中，在每个晶片的区域上制造监视电路。 监测电路包括代表位于晶片的管芯区域中的类似器件的代表性器件。 如果存在于代表性装置中的缺陷有助于产生噪声，从而导致在所选代表装置中可测量的差分信号的不平衡。 使用共模电压作为参考来测量不平衡的数字化电路将差分信号数字化为数字信号，数字信号表示由缺陷产生的噪声。 数字信号以可配置的时间间隔存储以形成数字比特流。 将数字比特流与参考进行比较，以确定失败是否在允许的范围内。
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40.发明申请METHOD AND SYSTEM FOR ENTRY AND VERIFICATION OF PARASITIC DESIGN CONSTRAINTS FOR ANALOG INTEGRATED CIRCUITS 有权用于模拟集成电路的PARASITIC设计约束的输入和验证方法与系统公开(公告)号：US20090265672A1
公开(公告)日：2009-10-22
申请号：US12103961
申请日：2008-04-16
IPC分类号： G06F17/50
CPC分类号： G06F17/5063
摘要： A method of designing an analog integrated circuit (IC), a parasitic constraint analyzer and a method of determining a layout of an analog IC complies with parasitic constraints. In one embodiment, the method of designing an analog IC includes: (1) creating a schematic of an analog integrated circuit based on a set of specifications, (2) attaching parasitic constraints to the schematic, (3) creating a layout of the analog integrated circuit based on the schematic including the parasitic constraints, (4) extracting parasitic values from parasitic elements of the layout and (5) comparing the extracted parasitic values with the parasitic constraints to verify compliance therewith.
摘要翻译： 设计模拟集成电路（IC）的方法，寄生约束分析器和确定模拟IC的布局的方法符合寄生约束。 在一个实施例中，设计模拟IC的方法包括：（1）基于一组规范创建模拟集成电路的示意图，（2）将附加约束附加到原理图，（3）创建模拟 基于包括寄生约束的示意图的集成电路，（4）从布局的寄生元件提取寄生值，以及（5）将所提取的寄生值与寄生约束进行比较以验证其符合性。
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