公开(公告)号：US06214695B1

公开(公告)日：2001-04-10

申请号：US09291043

申请日：1999-04-14

申请人： Yasuo Inoue ,  Yasuyoshi Itoh ,  Katsuyuki Horita

发明人： Yasuo Inoue ,  Yasuyoshi Itoh ,  Katsuyuki Horita

IPC分类号： H01L2176

CPC分类号： H01L21/76229

摘要： An object is to obtain a method of manufacturing semiconductor devices having trench isolation structure which accomplishes simplification of manufacturing process without deterioration of polishing uniformity. After a silicon oxide film (5) is deposited an HDP-CVD method, a polysilicon film (6) is deposited to such a thickness that the polysilicon film (6) on upper regions of raised areas is removed and the polysilicon film (6) in recessed areas remains in a first CMP process and that the polysilicon film (6) serves as a mask in a later etching process. Subsequently, the first CMP process is performed and the etching process to the silicon oxide film (5) is performed by using the polysilicon film (6) after the first CMP process as a mask to remove the silicon oxide film (5) in the upper regions of the raised areas, and a second CMP process is further performed to planarize the semiconductor substrate (1).

摘要翻译： 本发明的目的是获得一种制造具有沟槽隔离结构的半导体器件的方法，其实现了制造工艺的简化，而不会降低抛光均匀性。 在通过HDP-CVD法沉积氧化硅膜（5）之后，沉积多晶硅膜（6），使得去除凸起区域的上部区域上的多晶硅膜（6），并将多晶硅膜（6） 在凹陷区域保留在第一CMP工艺中，并且多晶硅膜（6）在稍后的蚀刻工艺中用作掩模。 随后，执行第一CMP处理，并且在第一CMP处理之后通过使用多晶硅膜（6）作为掩模来执行对氧化硅膜（5）的蚀刻处理，以去除上部的氧化硅膜（5） 并且进一步执行第二CMP处理以使半导体衬底（1）平坦化。

公开(公告)号：US09029951B2

公开(公告)日：2015-05-12

申请号：US13555184

申请日：2012-07-22

申请人： Katsuyuki Horita ,  Toshiaki Iwamatsu ,  Hideki Makiyama

发明人： Katsuyuki Horita ,  Toshiaki Iwamatsu ,  Hideki Makiyama

IPC分类号： H01L27/12 ,  H01L21/265 ,  H01L21/84 ,  H01L27/02 ,  H01L27/11 ,  G11C11/412 ,  H01L29/786 ,  H01L21/74

CPC分类号： H01L27/1203 ,  G11C11/412 ,  H01L21/2652 ,  H01L21/743 ,  H01L21/84 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/1104 ,  H01L27/1108 ,  H01L29/78648

摘要： A semiconductor device with an SRAM memory cell having improved characteristics. Below an active region in which a driver transistor including a SRAM is placed, an n type back gate region surrounded by an element isolation region is provided via an insulating layer. It is coupled to the gate electrode of the driver transistor. A p well region is provided below the n type back gate region and at least partially extends to a position deeper than the element isolation region. It is fixed at a grounding potential. Such a configuration makes it possible to control the threshold potential of the transistor to be high when the transistor is ON and to be low when the transistor is OFF; and control so as not to apply a forward bias to the PN junction between the p well region and the n type back gate region.

摘要翻译： 具有SRAM存储单元的具有改进特性的半导体器件。 在其中放置包括SRAM的驱动器晶体管的有源区域之下，经由绝缘层提供由元件隔离区域包围的n型背栅极区域。 它耦合到驱动晶体管的栅电极。 p型阱区域设置在n型背栅区域的下方，并且至少部分延伸到比元件隔离区域更深的位置。 它固定在接地电位。 这样的结构使得可以在晶体管导通时控制晶体管的阈值电位为高，而在晶体管截止时为低电平; 并且控制为不对p阱区域和n型背栅极区域之间的PN结施加正向偏压。

公开(公告)号：US08384187B2

公开(公告)日：2013-02-26

申请号：US12765571

申请日：2010-04-22

申请人： Mahito Sawada ,  Tatsunori Kaneoka ,  Katsuyuki Horita

发明人： Mahito Sawada ,  Tatsunori Kaneoka ,  Katsuyuki Horita

IPC分类号： H01L21/762

CPC分类号： H01L29/0653 ,  H01L21/02164 ,  H01L21/02222 ,  H01L21/02282 ,  H01L21/02337 ,  H01L21/3105 ,  H01L21/76205 ,  H01L21/76229 ,  H01L27/088

摘要： To provide a semiconductor device provided with an element isolation structure capable of hindering an adverse effect on electric characteristics of a semiconductor element, and a method of manufacturing the same. The thickness of a first silicon oxide film left in a shallow trench isolation having a relatively narrow width is thinner than the first silicon oxide film left in a shallow trench isolation having a relatively wide width. A second silicon oxide film (an upper layer) having a relatively high compressive stress by an HDP-CVD method is more thickly laminated over the first silicon oxide film in a lower layer by a thinned thickness of the first silicon oxide film. The compressive stress of an element isolation oxide film finally formed in a shallow trench isolation having a relatively narrow width is more enhanced.

摘要翻译： 提供一种具有能够阻碍对半导体元件的电特性的不利影响的元件隔离结构的半导体器件及其制造方法。 留在具有相对窄的宽度的浅沟槽隔离中的第一氧化硅膜的厚度比留在具有较宽宽度的浅沟槽隔离中的第一氧化硅膜薄。 通过HDP-CVD法具有相对高的压缩应力的第二氧化硅膜（上层）通过第一氧化硅膜的厚度较薄地层叠在下层的第一氧化硅膜上。 最终形成在具有相对窄的宽度的浅沟槽隔离中的元件隔离氧化膜的压缩应力被更强化。

公开(公告)号：US20120208346A1

公开(公告)日：2012-08-16

申请号：US13363312

申请日：2012-01-31

申请人： Masaru KADOSHIMA ,  Hiroshi Umeda ,  Tatsunori Kaneoka ,  Katsuyuki Horita

发明人： Masaru KADOSHIMA ,  Hiroshi Umeda ,  Tatsunori Kaneoka ,  Katsuyuki Horita

IPC分类号： H01L21/762

CPC分类号： H01L21/76229

摘要： A polysilazane film is formed over the main surface of a semiconductor substrate in such a manner that the upper surface level of the polysilazane film buried in a trench of 0.2 μm or less in width becomes higher than that of a pad insulating film and the upper surface level of the polysilazane film buried in a trench of 1.0 μm or more in width becomes lower than that of the pad insulating film. Then, heat treatment is conducted at 300° C. or more to convert the polysilazane film into a first buried film made of silicon oxide (SiO2) and remove a void in the upper portion of the narrower trench.

摘要翻译： 在半导体衬底的主表面上形成聚硅氮烷膜，使得掩埋在宽度为0.2μm以下的沟槽中的聚硅氮烷膜的上表面水平高于衬垫绝缘膜的上表面水平， 埋入宽度为1.0μm以上的沟槽中的聚硅氮烷膜的水平比焊垫绝缘膜低。 然后，在300℃以上进行热处理，将聚硅氮烷膜转换为由氧化硅（SiO 2）构成的第一掩埋膜，并且在较窄的沟槽的上部除去空隙。

公开(公告)号：US07244655B2

公开(公告)日：2007-07-17

申请号：US11292360

申请日：2005-12-02

申请人： Yoshinori Tanaka ,  Katsuyuki Horita ,  Heiji Kobayashi

发明人： Yoshinori Tanaka ,  Katsuyuki Horita ,  Heiji Kobayashi

IPC分类号： H01L21/336

CPC分类号： H01L27/10873 ,  H01L21/26586 ,  H01L27/10817 ,  H01L27/10894 ,  H01L27/10897 ,  H01L29/78

摘要： A method of manufacturing a semiconductor device is provided that can suppress impurity concentration reduction in a doped channel region arising from formation of a gate insulating film. With a silicon oxide film (20) and a silicon nitride film (21) being formed, p-type impurity ions (231, 232) are implanted in a Y direction from diagonally above. As for an implant angle α of the ion implantation, an implant angle is adopted that satisfies the relationship tan−1(W2/T)

摘要翻译： 提供一种制造半导体器件的方法，其可以抑制由栅极绝缘膜形成引起的掺杂沟道区域中的杂质浓度降低。 在形成氧化硅膜（20）和氮化硅膜（21）的情况下，将p型杂质离子（23×23×23×2×××××××××××××） 方向从对角线上方。 对于离子注入的注入角度α，采用满足关系tanθ-1（W 2 / T）<α<= TAN 的注入角度 （W 1 / T），其中W 1是第一部分（21 <1> 1）与第四部分（21 <4>）之间的间隔，第三部分 （21,33）和第六部分（21×6）; W 2是第二部分（21 ... 2）与第五部分（21 ... 5）之间的间隔; T是氧化硅膜（20）和氮化硅膜（21）的总膜厚。 当将注入角度α控制在该范围内时，将杂质离子（23,23,23）注入到第二侧表面（10 A 2 / SUB>）和通过氧化硅膜（13）的第五侧表面（10 A 5 S）。

公开(公告)号：US06661066B2

公开(公告)日：2003-12-09

申请号：US09401849

申请日：1999-09-22

申请人： Takashi Kuroi ,  Yasuyoshi Itoh ,  Katsuyuki Horita ,  Katsuomi Shiozawa

发明人： Takashi Kuroi ,  Yasuyoshi Itoh ,  Katsuyuki Horita ,  Katsuomi Shiozawa

IPC分类号： H01L31119

CPC分类号： H01L29/66553 ,  H01L21/26586 ,  H01L21/28088 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659

摘要： A semiconductor device and manufacturing method including a MOSFET having a trench-type element isolation structure (2) formed on a main surface of a semiconductor substrate (1). A pair of extensions (3) and source/drain regions (4) are selectively formed in the main surface so as to face each other through a channel region (50), a silicon oxide film (5) is formed on the trench-type element isolation structure (2) and on the source/drain regions (4) through a silicon oxide film (12), sidewalls (6) are formed on sides of the silicon oxide film (5), a gate insulating film (7) is formed on the main surface in a part where the channel region (50) is formed and a gate electrode (8) is formed to fill a recessed portion in an inversely tapered shape formed by the sides of the sidewalls (6) and the upper surface of the gate insulating film (7).

摘要翻译： 一种半导体器件和制造方法，包括形成在半导体衬底（1）的主表面上的沟槽型元件隔离结构（2）的MOSFET。 在主表面中选择性地形成一对延伸部（3）和源极/漏极区域（4），以便通过沟道区域（50）彼此面对，在沟槽型（5）上形成氧化硅膜 元件隔离结构（2），并且通过氧化硅膜（12）在源极/漏极区域（4）上，在氧化硅膜（5）的侧面上形成侧壁（6），栅极绝缘膜（7）为 形成在形成有沟道区域（50）的部分的主表面上，并且形成栅电极（8）以填充由侧壁（6）的侧面和上表面形成的倒锥形状的凹部 的栅极绝缘膜（7）。

公开(公告)号：US06372604B1

公开(公告)日：2002-04-16

申请号：US09860505

申请日：2001-05-21

申请人： Maiko Sakai ,  Takashi Kuroi ,  Katsuyuki Horita

发明人： Maiko Sakai ,  Takashi Kuroi ,  Katsuyuki Horita

IPC分类号： H01L2176

CPC分类号： H01L21/76232

摘要： There is provided a method for forming a trench type element isolation structure wherein no recess develops in the edge part of an imbedded oxide film of a trench type element isolation. Thermal oxidation films having higher etching resistance than the CVD film are formed not only on the surroundings of the imbedded oxide film inside the groove formed on the silicon substrate but also on the lateral sides of the imbedded oxide film projecting upward from the silicon substrate surface.

摘要翻译： 提供了一种形成沟槽型元件隔离结构的方法，其中在沟槽型元件隔离的嵌入式氧化物膜的边缘部分中不形成凹坑。不仅仅在CVD膜上形成具有比CVD膜更高的耐蚀刻性的热氧化膜 嵌入的氧化膜的周围形成在硅基板上的槽内，而且在从硅衬底表面向上突出的嵌入氧化膜的侧面上。

公开(公告)号：US06303432B1

公开(公告)日：2001-10-16

申请号：US09411386

申请日：1999-10-04

申请人： Katsuyuki Horita ,  Takashi Kuroi ,  Yasuyoshi Itoh ,  Katsuomi Siozawa

发明人： Katsuyuki Horita ,  Takashi Kuroi ,  Yasuyoshi Itoh ,  Katsuomi Siozawa

IPC分类号： H01L218242

CPC分类号： H01L27/10894 ,  H01L21/76224 ,  H01L21/823835 ,  H01L21/823878 ,  H01L27/10852 ,  H01L27/10873

摘要： There is described a method of manufacturing a semiconductor device, wherein a DRAM memory cell and a logic circuit are fabricated on a single semiconductor substrate, which method enables improvements in the refresh characteristics of the DRAM memory cell by preventing a leakage current from developing and enables improvements in the reliability of the semiconductor device, reduces power consumption, and enables improvements in the performance and processing speed of integrated circuits by assembly of the integrated circuits into a single chip. After formation of a polysilicon layer which is to act as gate electrodes, silicon nitride films are formed so as to cover source/drain regions of the DRAM memory cell and to cause other source/drain regions and the polysilicon layer to be exposed. A metal silicide layer is formed on the semiconductor substrate by means of self-aligned silicide technique.

摘要翻译： 描述了制造半导体器件的方法，其中在单个半导体衬底上制造DRAM存储单元和逻辑电路，该方法能够通过防止漏电流显影而提高DRAM存储单元的刷新特性，并使能 半导体器件的可靠性的提高，功耗降低，并且通过将集成电路组装成单个芯片，能够提高集成电路的性能和处理速度。 在形成用作栅电极的多晶硅层之后，形成氮化硅膜以覆盖DRAM存储单元的源极/漏极区域，并引起其它源极/漏极区域和多晶硅层的暴露。 通过自对准硅化物技术在半导体衬底上形成金属硅化物层。

公开(公告)号：US06265743B1

公开(公告)日：2001-07-24

申请号：US08963764

申请日：1997-11-04

申请人： Maiko Sakai ,  Takashi Kuroi ,  Katsuyuki Horita

发明人： Maiko Sakai ,  Takashi Kuroi ,  Katsuyuki Horita

IPC分类号： H01L27108

CPC分类号： H01L21/76232

摘要： There is provided a trench type element isolation structure wherein no recess develops in the edge part of an imbedded oxide film of a trench type element isolation. Thermal oxidation films having higher etching resistance than a CVD film are formed not only on the surroundings of the imbedded oxide film inside the groove formed on the silicon substrate but also on the lateral sides of the imbedded oxide film projecting upward from the silicon substrate surface.

摘要翻译： 提供了沟槽型元件隔离结构，其中在沟槽型元件隔离的嵌入式氧化物膜的边缘部分中不形成凹陷。 不仅在形成于硅基板上的槽内的嵌入氧化膜的周围，而且在从硅衬底表面向上突出的嵌入氧化膜的侧面上形成具有比CVD膜更高的耐蚀刻性的热氧化膜。

公开(公告)号：US5889335A

公开(公告)日：1999-03-30

申请号：US28112

申请日：1998-02-23

申请人： Takashi Kuroi ,  Maiko Sakai ,  Katsuyuki Horita ,  Hirokazu Sayama

发明人： Takashi Kuroi ,  Maiko Sakai ,  Katsuyuki Horita ,  Hirokazu Sayama

IPC分类号： H01L21/76 ,  H01L21/027 ,  H01L21/3213 ,  H01L21/762 ,  H01L21/8242 ,  H01L23/544 ,  H01L27/108 ,  H01L21/383

CPC分类号： H01L23/544 ,  H01L21/0274 ,  H01L21/32139 ,  H01L21/76229 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  Y10S438/975

摘要： The present invention provides a semiconductor device which includes trench-type element isolation which performs accurate alignment without deteriorating a device capability, and a method of manufacturing such a semiconductor device. Since a dummy gate electrode (14A) is formed in an edge proximity region of a trench (10A), a structure which does not create an etching remainder is realized. In addition, since a height difference is provided in a surface of the dummy gate electrode (14A) in such a manner that the height difference reflects a preliminary height difference between a surface of a silicon oxide films (2A) and a surface of a silicon substrate (1), it is possible to use the dummy gate electrode itself (14A) as an alignment mark.

摘要翻译： 本发明提供一种半导体器件，其包括沟槽型元件隔离，其在不劣化器件能力的情况下进行精确对准，以及制造这种半导体器件的方法。 由于在沟槽（10A）的边缘邻近区域中形成虚拟栅电极（14A），所以实现了不产生蚀刻余量的结构。 此外，由于在虚拟栅极电极（14A）的表面上设置高差，使得高度差反映了氧化硅膜（2A）的表面和硅表面之间的预备高度差 基板（1），可以使用伪栅电极本身（14A）作为对准标记。