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公开(公告)号：US06303432B1
公开(公告)日：2001-10-16
申请号：US09411386
申请日：1999-10-04
IPC分类号： H01L218242
CPC分类号： H01L27/10894 , H01L21/76224 , H01L21/823835 , H01L21/823878 , H01L27/10852 , H01L27/10873
摘要： There is described a method of manufacturing a semiconductor device, wherein a DRAM memory cell and a logic circuit are fabricated on a single semiconductor substrate, which method enables improvements in the refresh characteristics of the DRAM memory cell by preventing a leakage current from developing and enables improvements in the reliability of the semiconductor device, reduces power consumption, and enables improvements in the performance and processing speed of integrated circuits by assembly of the integrated circuits into a single chip. After formation of a polysilicon layer which is to act as gate electrodes, silicon nitride films are formed so as to cover source/drain regions of the DRAM memory cell and to cause other source/drain regions and the polysilicon layer to be exposed. A metal silicide layer is formed on the semiconductor substrate by means of self-aligned silicide technique.
摘要翻译： 描述了制造半导体器件的方法，其中在单个半导体衬底上制造DRAM存储单元和逻辑电路，该方法能够通过防止漏电流显影而提高DRAM存储单元的刷新特性，并使能 半导体器件的可靠性的提高，功耗降低，并且通过将集成电路组装成单个芯片，能够提高集成电路的性能和处理速度。 在形成用作栅电极的多晶硅层之后，形成氮化硅膜以覆盖DRAM存储单元的源极/漏极区域，并引起其它源极/漏极区域和多晶硅层的暴露。 通过自对准硅化物技术在半导体衬底上形成金属硅化物层。
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公开(公告)号：US20060027883A1
公开(公告)日：2006-02-09
申请号：US11241921
申请日：2005-10-04
IPC分类号： H01L29/94
CPC分类号： H01L29/66553 , H01L21/26586 , H01L21/28088 , H01L21/28114 , H01L29/42376 , H01L29/4966 , H01L29/517 , H01L29/66545 , H01L29/6659
摘要： An object is to obtain a semiconductor device in which channel length is reduced without increasing the gate resistance to realize higher operation speed and its manufacturing method. An MOSFET has a trench-type element isolation structure (2) formed in the main surface of a semiconductor substrate (1), a pair of extensions (3) and source/drain regions (4) selectively formed in the main surface of the semiconductor substrate (1) to face each other through a channel region (50), a silicon oxide film (5) formed on the trench-type element isolation structure (2) and on the source/drain regions (4) through a silicon oxide film (12), sidewalls (6) formed on sides of the silicon oxide film (5), a gate insulating film (7) formed on the main surface of the semiconductor substrate (1) in the part in which the channel region (50) is formed, and a gate electrode (8) formed to fill a recessed portion in an inversely tapered form formed by the sides of the sidewalls (6) and the upper surface of the gate insulating film (7).
摘要翻译： 本发明的目的是获得其中通道长度减小而不增加栅极电阻以实现更高的操作速度的半导体器件及其制造方法。 MOSFET具有形成在半导体衬底（1）的主表面中的沟槽型元件隔离结构（2），在半导体的主表面中选择性地形成的一对延伸部（3）和源极/漏极区域（4） 衬底（1）通过沟道区域（50）彼此面对，通过硅氧化膜形成在沟槽型元件隔离结构（2）上和源极/漏极区域（4）上的氧化硅膜（5） （12），形成在氧化硅膜（5）的侧面上的侧壁（6），形成在半导体衬底（1）的主表面上的沟道区域（50）的部分中的栅极绝缘膜（7） 以及形成为以由侧壁（6）的侧面和栅极绝缘膜（7）的上表面形成的倒锥形状填充凹部的栅电极（8）。
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3.发明授权Semiconductor device including inversely tapered gate electrode and manufacturing method thereof 失效包括反锥形栅电极的半导体器件及其制造方法公开(公告)号：US06661066B2
公开(公告)日：2003-12-09
申请号：US09401849
申请日：1999-09-22
IPC分类号： H01L31119
CPC分类号： H01L29/66553 , H01L21/26586 , H01L21/28088 , H01L21/28114 , H01L29/42376 , H01L29/4966 , H01L29/517 , H01L29/66545 , H01L29/6659
摘要： A semiconductor device and manufacturing method including a MOSFET having a trench-type element isolation structure (2) formed on a main surface of a semiconductor substrate (1). A pair of extensions (3) and source/drain regions (4) are selectively formed in the main surface so as to face each other through a channel region (50), a silicon oxide film (5) is formed on the trench-type element isolation structure (2) and on the source/drain regions (4) through a silicon oxide film (12), sidewalls (6) are formed on sides of the silicon oxide film (5), a gate insulating film (7) is formed on the main surface in a part where the channel region (50) is formed and a gate electrode (8) is formed to fill a recessed portion in an inversely tapered shape formed by the sides of the sidewalls (6) and the upper surface of the gate insulating film (7).
摘要翻译： 一种半导体器件和制造方法，包括形成在半导体衬底（1）的主表面上的沟槽型元件隔离结构（2）的MOSFET。 在主表面中选择性地形成一对延伸部（3）和源极/漏极区域（4），以便通过沟道区域（50）彼此面对，在沟槽型（5）上形成氧化硅膜 元件隔离结构（2），并且通过氧化硅膜（12）在源极/漏极区域（4）上，在氧化硅膜（5）的侧面上形成侧壁（6），栅极绝缘膜（7）为 形成在形成有沟道区域（50）的部分的主表面上，并且形成栅电极（8）以填充由侧壁（6）的侧面和上表面形成的倒锥形状的凹部 的栅极绝缘膜（7）。
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4.发明授权Semiconductor device achieving reduced wiring length and reduced wiring delay by forming first layer wiring and gate upper electrode in same wire layer 失效半导体器件通过在相同的线层中形成第一层布线和栅极上电极来实现缩短的布线长度并减少布线延迟公开(公告)号：US06548871B1
公开(公告)日：2003-04-15
申请号：US09543349
申请日：2000-04-05
IPC分类号： H01L2976
CPC分类号： H01L21/76895 , H01L21/76802 , H01L21/823475 , H01L23/522 , H01L23/535 , H01L29/66545 , H01L2924/0002 , H01L2924/00
摘要： Two source/drain regions (20) belonging to separate elements which are adjacent to each other are connected through a metal layer (14) having the same height as a height of a metal layer (10) forming a part of a gate electrode. In a manufacturing process, an insulating layer (8) is made of other material than and inserted between two insulating layers (7) and (16). The two insulating layers (7) and (16)function as molds for burying the metal layers (10), (14) and (15) therein and made of the same material. The metal layer (14) can therefore be formed at the same height as the height of the metal layer (10). Accordingly, portions to be connected through a wiring which are provided at a comparatively short distance are connected while reducing a wiring capacity.
摘要翻译： 属于彼此相邻的分离元件的两个源极/漏极区域（20）通过与形成栅电极的一部分的金属层（10）的高度相同的高度的金属层（14）连接。 在制造过程中，绝缘层（8）由除两个绝缘层（7）和（16）之外的其它材料制成。 两个绝缘层（7）和（16）作为用于将金属层（10），（14）和（15）埋入其中并由相同材料制成的模具。 因此，金属层（14）可以形成在与金属层（10）的高度相同的高度。 因此，通过布置在较短距离处的布线而连接的部分被连接，同时降低布线能力。
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公开(公告)号：US06383884B1
公开(公告)日：2002-05-07
申请号：US09496057
申请日：2000-02-02
IPC分类号： H01L21336
CPC分类号： H01L29/66545 , H01L21/28247 , H01L29/66537
摘要： A semiconductor device includes a silicon substrate (1), a pair of isolating insulation films (9), a channel region (2), a pair of source/drain regions (3), a pair of silicon oxide films (4) formed on an upper surface of the silicon substrate (1) so as to overlie the source/drain regions (3), and a gate structure (8) formed in a first recess defined by the upper surface of the silicon substrate (1) over the channel region (2) and side surfaces of the pair of silicon oxide films (4). The gate structure (8) includes a gate oxide film (5) formed on the upper surface of the silicon substrate (1), a pair of silicon oxide films (6) formed on lower part of the side surfaces of the pair of silicon oxide films (4), and a metal film (7) filling a second recess surrounded by upper part of the side surfaces of the silicon oxide films (4), the silicon oxide films (6) and the gate oxide film (5). A method of manufacturing the semiconductor device is provided which attains reduction in gate length without the decrease in driving capability to accomplish the increase in operating speed.
摘要翻译： 半导体器件包括硅衬底（1），一对隔离绝缘膜（9），沟道区（2），一对源/漏区（3），一对氧化硅膜（4），形成在 硅衬底（1）的上表面覆盖在源极/漏极区（3）上，并且栅极结构（8）形成在由硅衬底（1）的上表面限定的第一凹部中，沟道 区域（2）和一对氧化硅膜（4）的侧表面。 栅极结构（8）包括形成在硅衬底（1）的上表面上的栅氧化膜（5），一对氧化硅膜（6），形成在该一对氧化硅的侧表面的下部 以及填充由氧化硅膜（4）的侧面的上部，氧化硅膜（6）和栅极氧化膜（5）所包围的第二凹部的金属膜（7）。 提供了一种制造半导体器件的方法，其在不降低驱动能力的情况下实现栅极长度的减小以实现操作速度的提高。
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6.发明授权Method of manufacturing semiconductor device including steps of forming both insulating film and epitaxial semiconductor on substrate 失效制造半导体器件的方法包括在衬底上形成绝缘膜和外延半导体的步骤公开(公告)号：US06737315B2
公开(公告)日：2004-05-18
申请号：US10212249
申请日：2002-08-06
IPC分类号： H01L218242
CPC分类号： H01L21/762 , H01L21/823481 , H01L23/544 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： A substrate surface (10S) is thermally oxidized to form an oxide film. The oxide film is patterned so that the substrate surface (10S) in an active region is exposed. An oxide film (20) is thereby provided. An exposed substrate surface (10S) is thermally oxidized, to form a thermal oxide film. This thermal oxide film is thereafter removed at least in an element forming region. A silicon film (41) is epitaxially grown on the exposed substrate surface (10S). Thereafter the silicon film (41) is polished by CMP to an extent that an upper surface of the silicon film after polishing is not more than an upper surface of the oxide film (20) in height. Next, the surface of the silicon film is thermally oxidized to form a thermal oxide film. After ion implantation of various types, this thermal oxide film is removed.
摘要翻译： 将基板表面（10S）热氧化以形成氧化膜。 图案化氧化膜，使得有源区域中的衬底表面（10S）暴露。 由此提供氧化膜（20）。 暴露的衬底表面（10S）被热氧化，以形成热氧化膜。 此后，至少在元件形成区域中除去该热氧化膜。 在暴露的基板表面（10S）上外延生长硅膜（41）。 此后，通过CMP对硅膜（41）进行抛光，使抛光后的硅膜的上表面的高度不超过氧化膜（20）的上表面。 接着，将硅膜的表面热氧化，形成热氧化膜。 在各种类型的离子注入之后，去除该热氧化膜。
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公开(公告)号：US06707099B2
公开(公告)日：2004-03-16
申请号：US10218444
申请日：2002-08-15
IPC分类号： H01L29792
CPC分类号： H01L29/66651 , H01L21/28123 , H01L29/1033
摘要： A semiconductor device less susceptible to inverse narrow channel effect and its manufacturing method are provided. A silicon nitride film (13) is adopted as element isolation regions; the silicon nitride film (13) has a smaller etch rate than a sacrificial silicon oxide film (7) which serves as a sacrificial layer during ion implantation (8). This prevents formation of recesses in the silicon nitride film (13) during the removal of the sacrificial silicon oxide film (7), which weakens the strength of the electric fields at the gate edges. Weakening the strength of the electric fields at the gate edges suppresses the inverse narrow channel effect, so that the MOS transistor offers a characteristic closer to a characteristic in which the threshold voltage keeps a constant value independently of the channel width. Thus an MOS transistor having a good characteristic can be manufactured.
摘要翻译： 提供了一种不易反向窄通道效应的半导体器件及其制造方法。 采用氮化硅膜（13）作为元件隔离区域; 氮化硅膜（13）具有比在离子注入期间用作牺牲层的牺牲氧化硅膜（7）更小的蚀刻速率（8）。 这样可以防止在去除牺牲氧化硅膜（7）期间在氮化硅膜（13）中形成凹陷，这削弱了栅极边缘处的电场强度。 削弱栅极边缘处的电场强度抑制了反向窄通道效应，使得MOS晶体管具有更接近阈值电压独立于沟道宽度保持恒定值的特性。 因此，可以制造具有良好特性的MOS晶体管。
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公开(公告)号：US06498077B2
公开(公告)日：2002-12-24
申请号：US09816519
申请日：2001-03-26
申请人： Shuuichi Ueno , Katsuyuki Horita , Takashi Kuroi
发明人： Shuuichi Ueno , Katsuyuki Horita , Takashi Kuroi
IPC分类号： H01L21425
CPC分类号： H01L29/1083 , H01L21/26586 , H01L27/10808 , H01L27/10829 , H01L27/10841 , H01L27/10873 , H01L29/1045 , H01L29/105 , H01L29/66537 , H01L29/66545 , H01L29/7836
摘要： Provided are a semiconductor device having a MOS transistor of a structure capable of obtaining a good characteristic particularly about assurance of resistance to punch-through and leak current reduction, as well as a method of manufacturing the same. That is, in addition to the usual MOS transistor structure, a channel dope region (1) is disposed at a predetermined depth so as to extend substantially the entire surface of a flat surface in a P well region (22) including a channel region. In the channel dope region (1), it is set so that the maximum value of the P type impurity concentration (MAX of P) ranges from 1×1018 to 1×1019, and the maximum value of the N type impurity concentration (MAX of N) of a source/drain region (31 (32)) is not less than 10% and not more than 100%. Note that the surface proximate region of the P well region (22) is to be beyond the object.
摘要翻译： 本发明提供一种半导体器件及其制造方法，该半导体器件具有能够获得特别是耐穿孔和漏电流降低的保证的良好特性的结构的MOS晶体管。 也就是说，除了通常的MOS晶体管结构之外，通道掺杂区域（1）以预定深度设置，以便在包括沟道区域的P阱区域（22）中的基本上平坦表面的整个表面上延伸。 在通道掺杂区域（1）中，将P型杂质浓度（P的最大值）的最大值设定为1×1018〜1×1019，N型杂质浓度的最大值（N的最大值）为 源极/漏极区域（31（32））不小于10％且不大于100％。 注意，P阱区域（22）的表面邻近区域将超出对象。
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公开(公告)号：US06399985B2
公开(公告)日：2002-06-04
申请号：US09750759
申请日：2001-01-02
IPC分类号： H01L2976
CPC分类号： H01L21/823481 , H01L21/26586 , H01L21/76229 , H01L21/76235 , H01L27/0207 , H01L29/41758
摘要： Provided are a semiconductor device that can obtain more output current without increasing the occupied area of a MOS transistor, and a method for manufacturing the same. MOS transistors (M11, M12) are electrically isolated by a trench isolation oxide film (21). The MOS transistor (M11) has a groove portion (GP) in which the width of the top is 20 nm to 80 nm and the depth is 50 nm to 150 nm. The groove portion (GP) is disposed at the boundary part between a trench isolation insulating film (22) and an active region (AR1) so as to surround the active region (AR1). A gate electrode (31A) is not only disposed above the active region (AR1) but also buried in the groove (GP) with a gate oxide film (30) interposed therebetween. Similarly, in the MOS transistor (M12), a groove portion (GP) is disposed at the boundary part between the trench isolation insulating film (21) and an active region (AR2) so as to surround the active region (AR2), and a gate electrode (32A) is also buried in the groove (GP) with the gate oxide film (30) interposed therebetween.
摘要翻译： 提供一种可以在不增加MOS晶体管的占用面积的情况下获得更多的输出电流的半导体器件及其制造方法。 MOS晶体管（M11，M12）通过沟槽隔离氧化膜（21）电隔离。 MOS晶体管（M11）具有其顶部宽度为20nm〜80nm，深度为50nm〜150nm的槽部（GP）。 沟槽部分（GP）设置在沟道隔离绝缘膜（22）和有源区域（AR1）之间的边界部分，以围绕有源区域（AR1）。 栅电极（31A）不仅设置在有源区（AR1）的上方，而且还以栅介质膜（30）插入槽（GP）中。 类似地，在MOS晶体管（M12）中，沟槽部分（GP）设置在沟道隔离绝缘膜（21）和有源区域（AR2）之间的边界部分以包围有源区域（AR2），并且 栅极电极（32A）也被埋置在沟槽（GP）中，栅氧化膜（30）插入其间。
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公开(公告)号：US08043918B2
公开(公告)日：2011-10-25
申请号：US12840430
申请日：2010-07-21
IPC分类号： H01L21/336
CPC分类号： H01L21/823475 , H01L21/743 , H01L21/76229 , H01L21/763 , H01L21/823481 , H01L21/823871 , H01L21/823878 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： To manufacture in high productivity a semiconductor device capable of securely achieving element isolation by a trench-type element isolation and capable of effectively preventing potentials of adjacent elements from affecting other nodes, a method of manufacturing the semiconductor device includes: a step of forming a first layer on a substrate; a step of forming a trench by etching the first layer and the substrate; a step of thermally oxidizing an inner wall of the trench; a step of depositing a first conductive film having a film thickness equal to or larger than one half of the trench width of the trench on the substrate including the trench; a step of removing a first conductive film from the first layer by a CMP method and keeping the first conductive film left in only the trench; a step of anisotropically etching the first conductive film within the trench to adjust the height of the conductive film to become lower than the height of the surface of the substrate; a step of depositing an insulating film on the first conductive film by the CVD method to embed the upper part of the first conductive film within the trench; a step of flattening the insulating film by the CMP method; and a step of removing the first layer.
摘要翻译： 为了以高生产率制造能够通过沟槽型元件隔离可靠地实现元件隔离并且能够有效地防止相邻元件的电位影响其他节点的半导体器件，制造半导体器件的方法包括：形成第一 层; 通过蚀刻第一层和衬底形成沟槽的步骤; 热氧化沟槽内壁的步骤; 在包括沟槽的衬底上沉积膜厚度等于或大于沟槽的沟槽宽度的一半的第一导电膜的步骤; 通过CMP方法从第一层除去第一导电膜并保持第一导电膜仅留在沟槽中的步骤; 在沟槽内各向异性蚀刻第一导电膜的步骤，以调节导电膜的高度，使其低于衬底表面的高度; 通过CVD法在第一导电膜上沉积绝缘膜以将第一导电膜的上部嵌入沟槽内的步骤; 通过CMP方法使绝缘膜平坦化的步骤; 以及去除第一层的步骤。
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